CHIP Simulation Results

Monday May 12 2025 18:42:29 UTC

GitHub Revision: `4f742bf`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.903m	2.752ms	1	1	100.00
		chip_sw_example_rom	1.563m	2.768ms	1	1	100.00
		chip_sw_example_manufacturer	2.499m	2.561ms	1	1	100.00
		chip_sw_example_concurrency	2.745m	2.790ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.055m	4.431ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.150m	4.558ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	9.739m	11.076ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.208h	35.262ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	8.069m	11.771ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.208h	35.262ms	1	1	100.00
		chip_csr_rw	3.150m	4.558ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.770s	141.675us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.982m	4.645ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.982m	4.645ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.982m	4.645ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.369m	4.743ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.369m	4.743ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.975m	4.819ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.173m	3.918ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.677m	4.327ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	15.526m	7.848ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	15.118m	8.205ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	10.836m	8.735ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	2.863m	5.729ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.863m	5.729ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.046m	3.814ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.529m	5.942ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.545m	5.224ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	16.871m	16.954ms	1	1	100.00
		chip_tap_straps_testunlock0	5.032m	5.318ms	1	1	100.00
		chip_tap_straps_rma	2.574m	3.932ms	1	1	100.00
		chip_tap_straps_prod	1.586m	2.284ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.729m	2.719ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	13.467m	9.413ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.153m	4.357ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.153m	4.357ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.792m	8.363ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	22.964m	17.875ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.324m	3.999ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.461m	5.809ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.053m	18.306ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.288m	3.339ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.204m	5.917ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.831m	2.731ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.130m	8.890ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.871m	3.510ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.532m	4.367ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.439m	2.784ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.822m	3.178ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	7.612m	5.014ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.737m	4.749ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.613m	2.543ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.737m	4.749ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.790m	2.619ms	1	1	100.00
		chip_sw_aes_smoketest	2.567m	2.632ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.100m	2.967ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.484m	2.422ms	1	1	100.00
		chip_sw_csrng_smoketest	2.087m	2.672ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.950m	3.975ms	1	1	100.00
		chip_sw_gpio_smoketest	2.722m	3.255ms	1	1	100.00
		chip_sw_hmac_smoketest	3.570m	3.374ms	1	1	100.00
		chip_sw_kmac_smoketest	2.836m	2.974ms	1	1	100.00
		chip_sw_otbn_smoketest	9.274m	5.614ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.095m	5.950ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.648m	6.309ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.751m	2.480ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.305m	2.638ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.618m	3.501ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.715m	2.482ms	1	1	100.00
		chip_sw_uart_smoketest	2.340m	3.127ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.353m	2.613ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	3.899m	3.862ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.894h	60.093ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	34.535m	14.990ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	17.480s		0	1	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.605m	3.705ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.628m	3.255ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.703h	53.494ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.799h	57.062ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	51.310s	2.438ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	51.310s	2.438ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.208h	35.262ms	1	1	100.00
		chip_same_csr_outstanding	31.266m	27.606ms	1	1	100.00
		chip_csr_hw_reset	2.055m	4.431ms	1	1	100.00
		chip_csr_rw	3.150m	4.558ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.208h	35.262ms	1	1	100.00
		chip_same_csr_outstanding	31.266m	27.606ms	1	1	100.00
		chip_csr_hw_reset	2.055m	4.431ms	1	1	100.00
		chip_csr_rw	3.150m	4.558ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	32.020s	553.356us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.800s	38.018us	1	1	100.00
		xbar_smoke_large_delays	1.023m	9.978ms	1	1	100.00
		xbar_smoke_slow_rsp	46.370s	5.289ms	1	1	100.00
		xbar_random_zero_delays	16.040s	275.829us	1	1	100.00
		xbar_random_large_delays	5.062m	54.537ms	1	1	100.00
		xbar_random_slow_rsp	4.109m	30.642ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	33.010s	1.314ms	1	1	100.00
		xbar_error_and_unmapped_addr	34.630s	1.546ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	18.410s	419.972us	1	1	100.00
		xbar_error_and_unmapped_addr	34.630s	1.546ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	13.990s	218.013us	1	1	100.00
		xbar_access_same_device_slow_rsp	4.485m	30.918ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	14.180s	229.646us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	2.071m	2.659ms	1	1	100.00
		xbar_stress_all_with_error	1.771m	5.760ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1.355m	220.469us	1	1	100.00
		xbar_stress_all_with_reset_error	3.317m	3.144ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	34.535m	14.990ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	31.963m	27.739ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	34.267m	15.395ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	15.787s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	16.907s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	14.485s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.719s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	12.722s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	12.676s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	13.255s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	13.248s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	14.219s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	13.027s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	13.633s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	13.666s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	13.791s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	13.367s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	22.461s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	13.151s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	17.315s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	18.946s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.970s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.893s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	19.142s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	29.526s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	18.889s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.911s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	20.449s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.838s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.821s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.874s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	20.777s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	30.309s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	13.317s		0	1	0.00
		rom_e2e_asm_init_dev	13.295s		0	1	0.00
		rom_e2e_asm_init_prod	21.130s		0	1	0.00
		rom_e2e_asm_init_prod_end	13.936s		0	1	0.00
		rom_e2e_asm_init_rma	15.160s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	33.676m	15.322ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	34.779m	14.582ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	33.656m	15.091ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	35.159m	15.878ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	44.871m	34.462ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	44.871m	34.462ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	1.933m	3.061ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.288m	3.339ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.407m	3.308ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.062m	3.041ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	26.666m	12.271ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	3.399m	3.549ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.120m	4.476ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.521m	5.320ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.798m	5.378ms	1	1	100.00
		chip_plic_all_irqs_10	4.376m	3.371ms	1	1	100.00
		chip_plic_all_irqs_20	5.764m	4.630ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.932m	3.811ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	15.858m	11.927ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.873m	5.427ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.028m	2.999ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.831m	12.528ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	12.267m	6.986ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	12.681m	6.987ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.825m	7.808ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.091h	255.666ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.890m	3.596ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.095m	5.950ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.890m	3.596ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.025m	9.611ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.025m	9.611ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.909m	6.304ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.946m	5.680ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.335m	5.563ms	1	1	100.00
		chip_sw_aes_idle	2.062m	3.041ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.268m	3.174ms	1	1	100.00
		chip_sw_kmac_idle	2.196m	3.025ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.476m	3.730ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.998m	4.370ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.046m	4.584ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	5.037m	5.316ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	9.719m	10.398ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.681m	4.113ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.323m	4.682ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.261m	4.026ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.222m	5.255ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.977m	4.702ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.485m	3.820ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.792m	8.363ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	8.190m	11.788ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.261m	4.026ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.222m	5.255ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.324m	3.999ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.461m	5.809ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.053m	18.306ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.288m	3.339ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.204m	5.917ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.831m	2.731ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.130m	8.890ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.871m	3.510ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.532m	4.367ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.439m	2.784ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.416m	2.741ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.885m	4.599ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.881m	7.282ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	43.792m	23.893ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.760m	3.286ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	3.035m	3.778ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	10.182m	8.795ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.865m	2.980ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.295m	4.756ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	19.252m	26.861ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	51.234m	34.499ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.792m	8.363ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.198m	4.572ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.552m	3.668ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.521m	5.320ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	12.267m	6.986ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	15.646m	7.272ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.304m	3.103ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.414m	5.567ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.949m	3.248ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	55.014m	23.975ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.890m	3.101ms	1	1	100.00
		chip_sw_edn_entropy_reqs	13.372m	7.509ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.890m	3.101ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	15.646m	7.272ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.706m	3.098ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	17.751m	20.986ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.500m	6.112ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.461m	5.809ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	4.715m	3.681ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.324m	3.999ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	57.369m	42.670ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	17.751m	20.986ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.403m	3.994ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	17.891m	9.071ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.035m	5.392ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	57.369m	42.670ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.035m	5.392ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.035m	5.392ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.035m	5.392ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.035m	5.392ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.521m	5.320ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.720m	6.914ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.348m	5.427ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.391m	5.250ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.391m	5.250ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.816m	3.039ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.831m	2.731ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.268m	3.174ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.521m	3.573ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	15.826m	7.588ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.865m	4.565ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.022m	4.934ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.654m	5.640ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.342m	4.438ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	17.891m	9.071ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.130m	8.890ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	27.001m	11.829ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	26.666m	12.271ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	34.769m	11.900ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.533m	2.629ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.831m	3.625ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.871m	3.510ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	17.891m	9.071ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	4.874m	4.864ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.897m	3.046ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	15.910m	7.956ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.196m	3.025ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.120m	4.476ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	16.871m	16.954ms	1	1	100.00
		chip_tap_straps_rma	2.574m	3.932ms	1	1	100.00
		chip_tap_straps_prod	1.586m	2.284ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.284m	3.457ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	4.874m	4.864ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	4.874m	4.864ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	4.874m	4.864ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	15.604m	8.543ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.035m	5.392ms	1	1	100.00
		chip_sw_flash_rma_unlocked	57.369m	42.670ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.333m	2.945ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.890m	6.851ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.955m	6.598ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	10.329m	6.586ms	1	1	100.00
		chip_sw_lc_ctrl_transition	4.874m	4.864ms	1	1	100.00
		chip_sw_keymgr_key_derivation	17.891m	9.071ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.606m	8.350ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	6.074m	6.018ms	1	1	100.00
		chip_prim_tl_access	2.720m	6.914ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	8.190m	11.788ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.681m	4.113ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.323m	4.682ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.261m	4.026ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.222m	5.255ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.977m	4.702ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.485m	3.820ms	1	1	100.00
		chip_tap_straps_dev	16.871m	16.954ms	1	1	100.00
		chip_tap_straps_rma	2.574m	3.932ms	1	1	100.00
		chip_tap_straps_prod	1.586m	2.284ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.427m	15.059ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.434m	3.681ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.405m	3.475ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.685m	3.436ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.484m	3.848ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	23.563m	33.345ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.427m	15.059ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.009h	47.621ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	55.675m	46.317ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	9.779m	8.864ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	56.578m	46.236ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	23.563m	33.345ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.115m	2.561ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.112m	1.899ms	1	1	100.00
		rom_volatile_raw_unlock	20.299s		0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	48.553m	16.591ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.053m	18.306ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.335m	5.563ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.335m	5.563ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.335m	5.563ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.843m	3.961ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	4.874m	4.864ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	17.751m	20.986ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.843m	3.961ms	1	1	100.00
		chip_sw_keymgr_key_derivation	17.891m	9.071ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.328m	3.341ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.781m	2.768ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	17.751m	20.986ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.843m	3.961ms	1	1	100.00
		chip_sw_keymgr_key_derivation	17.891m	9.071ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.328m	3.341ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.781m	2.768ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	4.874m	4.864ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.309m	5.448ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.284m	3.457ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.333m	2.945ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.890m	6.851ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.955m	6.598ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	10.329m	6.586ms	1	1	100.00
		chip_sw_lc_ctrl_transition	4.874m	4.864ms	1	1	100.00
		chip_prim_tl_access	2.720m	6.914ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.720m	6.914ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	16.602m	9.813ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.648m	6.778ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	15.095m	22.127ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.427m	6.752ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	4.735m	8.475ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.139m	5.859ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	17.663m	22.481ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	12.363m	12.614ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	8.025m	9.611ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	12.106m	10.107ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.195m	3.709ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.648m	6.778ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	5.062m	5.384ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	33.241m	28.687ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.594m	6.583ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	5.003m	7.076ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	22.675m	27.543ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.969m	7.593ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	13.716m	10.244ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	29.019m	28.658ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.071m	2.720ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.521m	5.320ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.606m	8.350ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.606m	8.350ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	13.716m	10.244ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	22.675m	27.543ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.195m	3.709ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.095m	5.950ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.840m	5.035ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.765m	3.929ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.425m	5.361ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	15.858m	11.927ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.462m	2.959ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.521m	5.320ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	12.681m	6.987ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.108m	4.727ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.726m	4.200ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.267m	2.462ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.781m	2.768ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.765m	3.929ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.765m	3.929ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	13.362m	12.950ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	12.679m	14.252ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.840m	5.035ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.048m	4.103ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.936m	7.036ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	2.574m	3.932ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	5.427m	15.059ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.798m	5.378ms	1	1	100.00
		chip_plic_all_irqs_10	4.376m	3.371ms	1	1	100.00
		chip_plic_all_irqs_20	5.764m	4.630ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.155m	2.394ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.377m	3.023ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	34.535m	14.990ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	4.555m	4.640ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.610m	3.267ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.473m	3.221ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.367m	2.860ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.328m	3.341ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.532m	4.367ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	6.446m	8.089ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.335m	9.231ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	6.074m	6.018ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.521m	5.320ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.153m	4.357ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.969m	7.593ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	18.966m	25.965ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	1.919m	3.259ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.429m	3.478ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.222m	4.292ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	18.966m	25.965ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	18.966m	25.965ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	35.804m	20.257ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	35.804m	20.257ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	5.557m	6.373ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	44.871m	34.462ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.370m	3.128ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.455m	3.479ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.439m	4.264ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.322m	3.738ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.811m	8.692ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.286h	31.453ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	29.724m	11.538ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.943m	2.831ms	1	1	100.00
V2		TOTAL			228	275	82.91
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.623m	2.311ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.383m	2.218ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.384h	72.170ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	5.716m	3.837ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.095m	11.346ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.657m	11.894ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.977m	10.912ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	57.385s		0	1	0.00
		rom_e2e_jtag_inject_dev	46.621s		0	1	0.00
		rom_e2e_jtag_inject_rma	1.126m		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.396s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.775m	5.596ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.993m	2.838ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	17.706m	7.368ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	24.938m	11.411ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	4.144m	2.724ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.697m	4.246ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.014m	2.256ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.337m	6.062ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.441m	5.236ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.880m	5.983ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	13.716m	10.244ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.095m	11.346ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.657m	11.894ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.977m	10.912ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.576m	5.089ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.521m	5.320ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.307h	37.732ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.307h	37.732ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.706m	3.734ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.369m	4.743ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	50.930m	19.143ms	1	1	100.00
V3		TOTAL			18	23	78.26
	Unmapped tests	chip_sival_flash_info_access	2.282m	3.102ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.348m	4.880ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.851m	2.500ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.191m	2.471ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	4.225m	3.687ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.418s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.205m	2.552ms	1	1	100.00
		TOTAL			272	325	83.69

Failure Buckets

Job returned non-zero exit code has 42 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.96840834268715420066993809519312240560325488685135166894283900375602160241892
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.145s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.110652197032728196471824132407215351082021554644818798237824410551429052116047
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log

      File "/nightly/runs/opentitan/rules/bitstreams.bzl", line 70, column 13, in _bitstreams_repo_impl
          fail("Bitstream cache not initialized properly.")
  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:71:10: //hw/bitstream:cw310_mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 3.017s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_dev.30761765631855875682131296580840240556895934787674289819869505239815005725787
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log

  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:71:10: //hw/bitstream:cw310_mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  Analyzing: target //sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv (1 packages loaded, 26279 targets configured)

  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 2.001s, Critical Path: 0.03s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_prod has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_prod.27039794938239471651033232378121682979340112482793841183075322815610779952443
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log

  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:71:10: //hw/bitstream:cw310_mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  Analyzing: target //sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv (0 packages loaded, 26279 targets configured)

  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 1.900s, Critical Path: 0.03s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_prod_end has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.28017302536933665444889925276782392900100619795542749724872198832329562398622
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log

  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:59:10: //hw/bitstream:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  Analyzing: target //sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv (0 packages loaded, 26279 targets configured)

  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 1.598s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 37 more tests.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.63467442674566303628305294601749678861049018654179558879320284441232685715070
    Line 433, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3267.441126 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3267.441126 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@89421) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.61725792876207388297181716505479436952023951160965829474340944758320491968304
Line 431, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3928.780072 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@89421) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3928.780072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.105375126998024415824774875116732084371420410776846199374497101977201798702270
    Line 438, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34462.335528 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34462.335528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.69932699164748820787663193584074958070045319094790951065931582165134029775028
    Line 411, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3548.503560 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
  UVM_INFO @ 3548.503560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.99603393145723564217340706615413554330181735830619582312867801613168677399343
    Line 417, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2998.599892 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2998.599892 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.16150414437025236575577707902924603494052640039865032990630721019814657659541
    Line 408, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 3102.999980 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 3102.999980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34051) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.114039280497084224988442910533425707746176192431415308750293655027145252221357
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2438.024420 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34051) { a_addr: 'h10478  a_data: 'h9d509808  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h36  a_opcode: 'h4  a_user: 'h19586  d_param: 'h0  d_source: 'h36  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2438.024420 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.26788099680331236008278676372788025601775877173176405339736633292277053824207
    Line 415, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3704.826500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3704.826500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.94996018125827392481683870434546934995501318849459816448760569060152381853867
    Line 421, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3254.764500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3254.764500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.46311344790189717868029451922446541456918910500519762786207157868179373073602
    Line 429, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 17875.232200 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 17875.232200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.91304008119004448357745042068051681372685431508506560143993583262570606775602
    Line 472, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3836.729159 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3836.729159 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```