ADC_CTRL Simulation Results

Tuesday May 13 2025 20:18:55 UTC

GitHub Revision: 81efe90

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	9.910s	5.902ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.830s	705.378us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.430s	450.001us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	9.050s	11.216ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.020s	1.126ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.940s	543.868us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.430s	450.001us	1	1	100.00
		adc_ctrl_csr_aliasing	3.020s	1.126ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	4.280m	162.482ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	3.439m	166.280ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	4.513m	326.927ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	15.242m	497.055ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	5.408m	372.264ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	15.124m	605.461ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	4.211m	595.574ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	16.426m	566.623ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	9.890s	5.219ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	12.060s	34.925ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	3.200m	117.044ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	4.321m	164.835ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.750s	332.664us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.640s	485.241us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.930s	529.033us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.930s	529.033us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.830s	705.378us	1	1	100.00
		adc_ctrl_csr_rw	2.430s	450.001us	1	1	100.00
		adc_ctrl_csr_aliasing	3.020s	1.126ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.760s	3.613ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.830s	705.378us	1	1	100.00
		adc_ctrl_csr_rw	2.430s	450.001us	1	1	100.00
		adc_ctrl_csr_aliasing	3.020s	1.126ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.760s	3.613ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	3.770s	4.715ms	1	1	100.00
		adc_ctrl_tl_intg_err	4.110s	9.248ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	4.110s	9.248ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	5.080s	8.565ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00