EDN Simulation Results

Tuesday May 13 2025 20:18:55 UTC

GitHub Revision: 81efe90

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.920s	181.859us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.610s	113.082us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.590s	21.780us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.280s	1.041ms	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.820s	51.687us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.080s	33.295us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.590s	21.780us	1	1	100.00
		edn_csr_aliasing	1.820s	51.687us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.070s	94.706us	1	1	100.00
V2	csrng_commands	edn_genbits	2.070s	94.706us	1	1	100.00
V2	genbits	edn_genbits	2.070s	94.706us	1	1	100.00
V2	interrupts	edn_intr	1.970s	31.460us	1	1	100.00
V2	alerts	edn_alert	2.120s	102.168us	1	1	100.00
V2	errs	edn_err	2.050s	51.028us	1	1	100.00
V2	disable	edn_disable	1.890s	39.362us	1	1	100.00
		edn_disable_auto_req_mode	1.890s	92.407us	1	1	100.00
V2	stress_all	edn_stress_all	2.380s	117.906us	1	1	100.00
V2	intr_test	edn_intr_test	1.540s	23.636us	1	1	100.00
V2	alert_test	edn_alert_test	1.760s	19.224us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.340s	205.439us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.340s	205.439us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.610s	113.082us	1	1	100.00
		edn_csr_rw	1.590s	21.780us	1	1	100.00
		edn_csr_aliasing	1.820s	51.687us	1	1	100.00
		edn_same_csr_outstanding	1.790s	36.461us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.610s	113.082us	1	1	100.00
		edn_csr_rw	1.590s	21.780us	1	1	100.00
		edn_csr_aliasing	1.820s	51.687us	1	1	100.00
		edn_same_csr_outstanding	1.790s	36.461us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	4.890s	1.240ms	1	1	100.00
		edn_tl_intg_err	2.240s	242.579us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	2.160s	16.423us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	2.120s	102.168us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.890s	1.240ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.890s	1.240ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.890s	1.240ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.890s	1.240ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.120s	102.168us	1	1	100.00
		edn_sec_cm	4.890s	1.240ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.120s	102.168us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.240s	242.579us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	22.880s	2.438ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00