| V1 |
smoke |
hmac_smoke |
2.660s |
71.085us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
hmac_csr_hw_reset |
1.620s |
54.017us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
hmac_csr_rw |
1.820s |
63.796us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
hmac_csr_bit_bash |
4.310s |
210.225us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
hmac_csr_aliasing |
5.150s |
1.193ms |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
hmac_csr_mem_rw_with_rand_reset |
3.170s |
70.173us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
hmac_csr_rw |
1.820s |
63.796us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
5.150s |
1.193ms |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
long_msg |
hmac_long_msg |
3.880s |
168.501us |
1 |
1 |
100.00 |
| V2 |
back_pressure |
hmac_back_pressure |
30.900s |
12.221ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
hmac_test_sha256_vectors |
3.159m |
31.714ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
6.296m |
50.383ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
5.891m |
23.312ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
6.970s |
258.325us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
8.650s |
3.155ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
12.070s |
310.308us |
1 |
1 |
100.00 |
| V2 |
burst_wr |
hmac_burst_wr |
18.620s |
2.659ms |
1 |
1 |
100.00 |
| V2 |
datapath_stress |
hmac_datapath_stress |
5.932m |
3.131ms |
1 |
1 |
100.00 |
| V2 |
error |
hmac_error |
18.240s |
5.897ms |
1 |
1 |
100.00 |
| V2 |
wipe_secret |
hmac_wipe_secret |
28.740s |
4.836ms |
1 |
1 |
100.00 |
| V2 |
save_and_restore |
hmac_smoke |
2.660s |
71.085us |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
3.880s |
168.501us |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
30.900s |
12.221ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
5.932m |
3.131ms |
1 |
1 |
100.00 |
|
|
hmac_burst_wr |
18.620s |
2.659ms |
1 |
1 |
100.00 |
|
|
hmac_stress_all |
3.478m |
79.524ms |
1 |
1 |
100.00 |
| V2 |
fifo_empty_status_interrupt |
hmac_smoke |
2.660s |
71.085us |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
3.880s |
168.501us |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
30.900s |
12.221ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
5.932m |
3.131ms |
1 |
1 |
100.00 |
|
|
hmac_wipe_secret |
28.740s |
4.836ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha256_vectors |
3.159m |
31.714ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
6.296m |
50.383ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
5.891m |
23.312ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
6.970s |
258.325us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
8.650s |
3.155ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
12.070s |
310.308us |
1 |
1 |
100.00 |
| V2 |
wide_digest_configurable_key_length |
hmac_smoke |
2.660s |
71.085us |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
3.880s |
168.501us |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
30.900s |
12.221ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
5.932m |
3.131ms |
1 |
1 |
100.00 |
|
|
hmac_burst_wr |
18.620s |
2.659ms |
1 |
1 |
100.00 |
|
|
hmac_error |
18.240s |
5.897ms |
1 |
1 |
100.00 |
|
|
hmac_wipe_secret |
28.740s |
4.836ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha256_vectors |
3.159m |
31.714ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
6.296m |
50.383ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
5.891m |
23.312ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
6.970s |
258.325us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
8.650s |
3.155ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
12.070s |
310.308us |
1 |
1 |
100.00 |
|
|
hmac_stress_all |
3.478m |
79.524ms |
1 |
1 |
100.00 |
| V2 |
stress_all |
hmac_stress_all |
3.478m |
79.524ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
hmac_alert_test |
1.670s |
14.621us |
1 |
1 |
100.00 |
| V2 |
intr_test |
hmac_intr_test |
1.430s |
71.142us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
hmac_tl_errors |
3.860s |
685.741us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
hmac_tl_errors |
3.860s |
685.741us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
hmac_csr_hw_reset |
1.620s |
54.017us |
1 |
1 |
100.00 |
|
|
hmac_csr_rw |
1.820s |
63.796us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
5.150s |
1.193ms |
1 |
1 |
100.00 |
|
|
hmac_same_csr_outstanding |
3.040s |
960.447us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
hmac_csr_hw_reset |
1.620s |
54.017us |
1 |
1 |
100.00 |
|
|
hmac_csr_rw |
1.820s |
63.796us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
5.150s |
1.193ms |
1 |
1 |
100.00 |
|
|
hmac_same_csr_outstanding |
3.040s |
960.447us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
17 |
17 |
100.00 |
| V2S |
tl_intg_err |
hmac_sec_cm |
1.810s |
39.382us |
1 |
1 |
100.00 |
|
|
hmac_tl_intg_err |
4.330s |
3.195ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
hmac_tl_intg_err |
4.330s |
3.195ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
write_config_and_secret_key_during_msg_wr |
hmac_smoke |
2.660s |
71.085us |
1 |
1 |
100.00 |
| V3 |
stress_reset |
hmac_stress_reset |
3.200s |
155.149us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
hmac_stress_all_with_rand_reset |
1.139m |
2.338ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
2 |
2 |
100.00 |
|
Unmapped tests |
hmac_directed |
2.680s |
894.100us |
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
28 |
28 |
100.00 |