I2C Simulation Results

Tuesday May 13 2025 20:18:55 UTC

GitHub Revision: `81efe90`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	49.770s	1.590ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	12.860s	1.705ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.510s	19.493us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.660s	25.550us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.120s	223.309us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.250s	144.706us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.180s	31.467us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.660s	25.550us	1	1	100.00
		i2c_csr_aliasing	2.250s	144.706us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.210s	220.424us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	8.514m	19.036ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	12.560s	1.121ms	1	1	100.00
V2	host_override	i2c_host_override	1.610s	30.737us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	43.560s	3.424ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	38.190s	4.414ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.680s	247.807us	1	1	100.00
		i2c_host_fifo_fmt_empty	8.850s	566.985us	1	1	100.00
		i2c_host_fifo_reset_rx	4.730s	770.511us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	55.380s	6.737ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	31.690s	4.348ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.590s	162.744us	0	1	0.00
V2	target_glitch	i2c_target_glitch	8.030s	8.698ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	2.529m	36.636ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	5.110s	1.513ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	6.990s	521.825us	1	1	100.00
		i2c_target_intr_smoke	7.620s	7.304ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.910s	283.804us	1	1	100.00
		i2c_target_fifo_reset_tx	1.880s	493.652us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	4.443m	39.128ms	1	1	100.00
		i2c_target_stress_rd	6.990s	521.825us	1	1	100.00
		i2c_target_intr_stress_wr	23.150s	8.401ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.080s	2.274ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	1.295m	2.529ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.010s	1.769ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.760s	750.001us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.240s	452.593us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.020s	170.018us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	12.560s	1.121ms	1	1	100.00
		i2c_host_perf_precise	2.950s	224.573us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	31.690s	4.348ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	4.040s	200.453us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.100s	576.681us	1	1	100.00
		i2c_target_nack_acqfull_addr	3.010s	568.599us	1	1	100.00
		i2c_target_nack_txstretch	2.280s	282.852us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	23.400s	770.961us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.840s	547.106us	1	1	100.00
V2	alert_test	i2c_alert_test	1.400s	14.309us	1	1	100.00
V2	intr_test	i2c_intr_test	1.630s	48.331us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.070s	44.458us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.070s	44.458us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.510s	19.493us	1	1	100.00
		i2c_csr_rw	1.660s	25.550us	1	1	100.00
		i2c_csr_aliasing	2.250s	144.706us	1	1	100.00
		i2c_same_csr_outstanding	1.890s	31.347us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.510s	19.493us	1	1	100.00
		i2c_csr_rw	1.660s	25.550us	1	1	100.00
		i2c_csr_aliasing	2.250s	144.706us	1	1	100.00
		i2c_same_csr_outstanding	1.890s	31.347us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.620s	699.809us	1	1	100.00
		i2c_sec_cm	1.640s	62.553us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.620s	699.809us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	7.680s	2.045ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.950s	306.679us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	10.060s	379.538us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.36571743793671520157348652975964608621641123158156829044423457123958966129046
    Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2044831869 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2044831869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.28550024867955314011472733373766412613781006233509882570775370949685337398229
    Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 379537586 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 379537586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.59334436383332944879081778952832542364896405668566655187413599627397259104378
Line 293, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 19036075000 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4550370

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.105913916222280203985731221031432701621735007545968045266788080522134276258581
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 306678985 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 306678985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 0.i2c_host_mode_toggle.53987882644938126425321220786545229570276064700187672144728878849999419907873
    Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
```
  UVM_ERROR @ 162743978 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------
```