KEYMGR Simulation Results

Tuesday May 13 2025 20:18:55 UTC

GitHub Revision: 81efe90

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	4.330s	253.879us	1	1	100.00
V1	random	keymgr_random	5.350s	267.145us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.870s	14.114us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.640s	32.804us	0	1	0.00
V1	csr_bit_bash	keymgr_csr_bit_bash	6.110s	2.898ms	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	6.740s	645.793us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.180s	157.297us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.640s	32.804us	0	1	0.00
		keymgr_csr_aliasing	6.740s	645.793us	1	1	100.00
V1		TOTAL			5	7	71.43
V2	cfgen_during_op	keymgr_cfg_regwen	3.100s	385.757us	1	1	100.00
V2	sideload	keymgr_sideload	3.010s	119.524us	1	1	100.00
		keymgr_sideload_kmac	4.530s	689.121us	1	1	100.00
		keymgr_sideload_aes	3.030s	159.341us	1	1	100.00
		keymgr_sideload_otbn	12.340s	1.502ms	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.780s	244.599us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.520s	79.511us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.150s	205.181us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.880s	576.763us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.290s	106.109us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.720s	38.572us	1	1	100.00
V2	stress_all	keymgr_stress_all	29.340s	1.843ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.520s	63.747us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.880s	70.866us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.600s	58.577us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.600s	58.577us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.870s	14.114us	1	1	100.00
		keymgr_csr_rw	1.640s	32.804us	0	1	0.00
		keymgr_csr_aliasing	6.740s	645.793us	1	1	100.00
		keymgr_same_csr_outstanding	2.290s	144.130us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.870s	14.114us	1	1	100.00
		keymgr_csr_rw	1.640s	32.804us	0	1	0.00
		keymgr_csr_aliasing	6.740s	645.793us	1	1	100.00
		keymgr_same_csr_outstanding	2.290s	144.130us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	4.680s	231.891us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	4.680s	231.891us	1	1	100.00
		keymgr_tl_intg_err	2.120s	86.259us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.610s	686.339us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.610s	686.339us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.610s	686.339us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.610s	686.339us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	1.900s	14.206us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	4.680s	231.891us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	4.680s	231.891us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	2.120s	86.259us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.610s	686.339us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.100s	385.757us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	5.350s	267.145us	1	1	100.00
		keymgr_csr_rw	1.640s	32.804us	0	1	0.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	5.350s	267.145us	1	1	100.00
		keymgr_csr_rw	1.640s	32.804us	0	1	0.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	5.350s	267.145us	1	1	100.00
		keymgr_csr_rw	1.640s	32.804us	0	1	0.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.520s	79.511us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.290s	106.109us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.290s	106.109us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	5.350s	267.145us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.060s	63.288us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	4.680s	231.891us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	4.680s	231.891us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	4.680s	231.891us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.700s	146.332us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.520s	79.511us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	4.680s	231.891us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	4.680s	231.891us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	4.680s	231.891us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.700s	146.332us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.700s	146.332us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	4.680s	231.891us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.700s	146.332us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	4.680s	231.891us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.700s	146.332us	1	1	100.00
V2S		TOTAL			4	6	66.67
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	5.630s	508.290us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	30	86.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 4 failures:

  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.6929300973562881488391686701842316794096476589794465949300830083833681326336
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
        UVM_ERROR @  14205549 ps: (keymgr_csr_assert_fpv.sv:446) [ASSERT FAILED] attest_sw_binding_3_rd_A
        UVM_INFO @  14205549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.3890838579410094339198182862317614333177185494649099967923935551810069867520
      Line 100, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
        UVM_ERROR @  86258955 ps: (keymgr_csr_assert_fpv.sv:421) [ASSERT FAILED] sealing_sw_binding_6_rd_A
        UVM_INFO @  86258955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_rw has 1 failures.

    • 0.keymgr_csr_rw.90982903260471570309849467917068079751930440054421214880732126792293597428309
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[6] & 'hffffffff)))'
        UVM_ERROR @  32804058 ps: (keymgr_csr_assert_fpv.sv:396) [ASSERT FAILED] sealing_sw_binding_1_rd_A
        UVM_INFO @  32804058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.67970631311701442270154637716573512167264325764257779475645398759003572425138
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
        UVM_ERROR @ 2897740344 ps: (keymgr_csr_assert_fpv.sv:406) [ASSERT FAILED] sealing_sw_binding_3_rd_A
        UVM_INFO @ 2897740344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---