KMAC/MASKED Simulation Results

Tuesday May 13 2025 20:18:55 UTC

GitHub Revision: 81efe90

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	15.700s	1.740ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.190s	52.409us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.890s	18.290us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.730s	503.260us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.150s	284.554us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.320s	183.191us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.890s	18.290us	1	1	100.00
		kmac_csr_aliasing	4.150s	284.554us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.690s	11.855us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.970s	59.279us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	41.752m	82.697ms	1	1	100.00
V2	burst_write	kmac_burst_write	7.554m	123.350ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.520s	2.440ms	1	1	100.00
		kmac_test_vectors_sha3_256	26.950s	4.171ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.175m	13.588ms	1	1	100.00
		kmac_test_vectors_sha3_512	12.950s	559.932us	1	1	100.00
		kmac_test_vectors_shake_128	27.658m	41.889ms	1	1	100.00
		kmac_test_vectors_shake_256	1.667m	10.199ms	1	1	100.00
		kmac_test_vectors_kmac	2.930s	322.263us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.840s	605.328us	1	1	100.00
V2	sideload	kmac_sideload	2.904m	36.575ms	1	1	100.00
V2	app	kmac_app	2.616m	15.602ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	23.710s	9.850ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.586m	8.770ms	1	1	100.00
V2	error	kmac_error	28.440s	1.874ms	1	1	100.00
V2	key_error	kmac_key_error	11.120s	6.180ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.220s	549.461us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	2.830s	281.966us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.810s	40.410us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	38.210s	18.997ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.140s	85.870us	1	1	100.00
V2	stress_all	kmac_stress_all	6.037m	96.500ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.610s	14.029us	1	1	100.00
V2	alert_test	kmac_alert_test	1.720s	38.510us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.200s	196.618us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.200s	196.618us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.190s	52.409us	1	1	100.00
		kmac_csr_rw	1.890s	18.290us	1	1	100.00
		kmac_csr_aliasing	4.150s	284.554us	1	1	100.00
		kmac_same_csr_outstanding	2.760s	91.910us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.190s	52.409us	1	1	100.00
		kmac_csr_rw	1.890s	18.290us	1	1	100.00
		kmac_csr_aliasing	4.150s	284.554us	1	1	100.00
		kmac_same_csr_outstanding	2.760s	91.910us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.290s	146.913us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.290s	146.913us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.290s	146.913us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.290s	146.913us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.080s	78.321us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	59.730s	7.576ms	1	1	100.00
		kmac_tl_intg_err	4.270s	187.174us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.270s	187.174us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.140s	85.870us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	15.700s	1.740ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.904m	36.575ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.290s	146.913us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	59.730s	7.576ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	59.730s	7.576ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	59.730s	7.576ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	15.700s	1.740ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.140s	85.870us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	59.730s	7.576ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	16.500s	1.685ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	15.700s	1.740ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	8.820s	647.989us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.32518393466489555162786297714055980757681956095111956928720242013139266965980
      Line 85, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 647989211 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 647989211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---