| V1 |
smoke |
kmac_smoke |
21.730s |
1.473ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
1.920s |
135.457us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
1.800s |
32.363us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
15.270s |
5.741ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
4.450s |
200.244us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
2.840s |
82.886us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
1.800s |
32.363us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
4.450s |
200.244us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
1.770s |
11.906us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.830s |
49.574us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
29.998m |
26.842ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
4.674m |
18.602ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
30.900s |
1.777ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
22.490s |
1.163ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
15.920s |
427.720us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
12.083m |
66.804ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
1.602m |
4.445ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
1.413m |
4.838ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
2.560s |
29.582us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
2.630s |
57.498us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
3.472m |
3.918ms |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
56.240s |
4.551ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
35.060s |
2.881ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
1.539m |
7.407ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
2.552m |
120.375ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
9.360s |
3.923ms |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
3.640s |
64.730us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
3.640s |
304.571us |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
22.380s |
4.266ms |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
14.380s |
5.550ms |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
2.710s |
49.500us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
22.483m |
27.269ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
1.700s |
14.692us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
1.670s |
169.638us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
3.880s |
733.775us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
3.880s |
733.775us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
1.920s |
135.457us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.800s |
32.363us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
4.450s |
200.244us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
2.350s |
102.280us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
1.920s |
135.457us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.800s |
32.363us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
4.450s |
200.244us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
2.350s |
102.280us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
2.040s |
46.027us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
2.040s |
46.027us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
2.040s |
46.027us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
2.040s |
46.027us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
3.760s |
278.084us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
18.440s |
2.910ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
4.450s |
190.062us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
4.450s |
190.062us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
2.710s |
49.500us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
21.730s |
1.473ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
3.472m |
3.918ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
2.040s |
46.027us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
18.440s |
2.910ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
18.440s |
2.910ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
18.440s |
2.910ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
21.730s |
1.473ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
2.710s |
49.500us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
18.440s |
2.910ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
2.328m |
17.427ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
21.730s |
1.473ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
1.968m |
7.672ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |