ROM_CTRL/64KB Simulation Results

Tuesday May 13 2025 20:18:55 UTC

GitHub Revision: 81efe90

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.990s 230.209us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 10.450s 683.390us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.050s 207.762us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.550s 815.054us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.430s 536.687us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.630s 1.149ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.050s 207.762us 1 1 100.00
rom_ctrl_csr_aliasing 7.430s 536.687us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 10.200s 300.381us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.350s 212.327us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.310s 761.952us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 22.200s 3.093ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 12.050s 711.821us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 5.870s 726.427us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 10.220s 557.031us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 10.220s 557.031us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 10.450s 683.390us 1 1 100.00
rom_ctrl_csr_rw 7.050s 207.762us 1 1 100.00
rom_ctrl_csr_aliasing 7.430s 536.687us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.330s 1.027ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 10.450s 683.390us 1 1 100.00
rom_ctrl_csr_rw 7.050s 207.762us 1 1 100.00
rom_ctrl_csr_aliasing 7.430s 536.687us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.330s 1.027ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.851m 11.403ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 37.040s 3.211ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.690m 811.785us 1 1 100.00
rom_ctrl_tl_intg_err 37.490s 843.431us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.690m 811.785us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.690m 811.785us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.851m 11.403ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.851m 11.403ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.851m 11.403ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.851m 11.403ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.851m 11.403ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.690m 811.785us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.690m 811.785us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.990s 230.209us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.990s 230.209us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.990s 230.209us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 37.490s 843.431us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.851m 11.403ms 1 1 100.00
rom_ctrl_kmac_err_chk 12.050s 711.821us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.851m 11.403ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.851m 11.403ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.851m 11.403ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 37.040s 3.211ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.690m 811.785us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.084m 17.796ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00