RV_DM/USE_JTAG_INTERFACE Simulation Results

Tuesday May 13 2025 20:18:55 UTC

GitHub Revision: 81efe90

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 5.740s 1.992ms 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.780s 118.642us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.080s 270.837us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 5.140s 7.236ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.900s 211.377us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 13.950s 3.999ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 10.870s 5.193ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.750s 47.046us 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 3.268m 105.016ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 3.330s 559.884us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 2.000s 199.425us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.900s 122.430us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.510s 198.070us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.670s 292.545us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 2.300s 643.604us 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.920s 71.709us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.050s 164.257us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 3.330s 559.884us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.840s 247.314us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.160s 1.203ms 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.900s 122.430us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 2.130s 122.517us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.970s 237.725us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.910s 392.472us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 28.700s 24.494ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 21.230s 6.348ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 2.020s 32.633us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 21.230s 6.348ms 1 1 100.00
rv_dm_csr_rw 2.910s 392.472us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 2.040s 135.697us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 2.010s 142.828us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 5.740s 1.992ms 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 2.040s 833.758us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.760s 384.073us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 2.020s 325.944us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.090s 385.038us 1 1 100.00
V2 sba rv_dm_sba_tl_access 4.290s 1.736ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 1.690s 117.745us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 2.540s 698.911us 0 1 0.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 10.070s 8.089ms 1 1 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.030s 484.638us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 2.070s 1.121ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 2.910s 823.808us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 2.140s 343.815us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 9.700s 11.444ms 0 1 0.00
rv_dm_tap_fsm_rand_reset 4.950s 329.554us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.750s 70.452us 1 1 100.00
V2 stress_all rv_dm_stress_all 6.760s 3.257ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.880s 98.326us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.740s 58.019us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.740s 58.019us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 21.230s 6.348ms 1 1 100.00
rv_dm_csr_hw_reset 2.970s 237.725us 1 1 100.00
rv_dm_csr_rw 2.910s 392.472us 1 1 100.00
rv_dm_same_csr_outstanding 7.430s 4.387ms 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 21.230s 6.348ms 1 1 100.00
rv_dm_csr_hw_reset 2.970s 237.725us 1 1 100.00
rv_dm_csr_rw 2.910s 392.472us 1 1 100.00
rv_dm_same_csr_outstanding 7.430s 4.387ms 1 1 100.00
V2 TOTAL 14 19 73.68
V2S tl_intg_err rv_dm_sec_cm 2.710s 572.846us 1 1 100.00
rv_dm_tl_intg_err 12.450s 3.384ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 12.450s 3.384ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 2.070s 1.121ms 1 1 100.00
rv_dm_debug_disabled 1.760s 145.951us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 2.070s 1.121ms 1 1 100.00
rv_dm_debug_disabled 1.760s 145.951us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 5.740s 1.992ms 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 1.760s 155.024us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.720s 85.631us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.720s 85.631us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 1.760s 155.024us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.810s 102.984us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.820s 18.629us 1 1 100.00
TOTAL 46 53 86.79

Failure Buckets