RV_TIMER Simulation Results

Tuesday May 13 2025 20:18:55 UTC

GitHub Revision: 81efe90

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.520s	32.197us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.470s	36.900us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.570s	81.950us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.080s	489.206us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.640s	39.376us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.680s	32.484us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.570s	81.950us	1	1	100.00
		rv_timer_csr_aliasing	1.640s	39.376us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	10.540s	66.365ms	1	1	100.00
V2	disabled	rv_timer_disabled	1.860s	372.711us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	42.480s	48.961ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	42.480s	48.961ms	1	1	100.00
V2	stress	rv_timer_stress_all	10.200s	13.294ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.440s	39.360us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.390s	12.732us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.420s	52.887us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.420s	52.887us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.470s	36.900us	1	1	100.00
		rv_timer_csr_rw	1.570s	81.950us	1	1	100.00
		rv_timer_csr_aliasing	1.640s	39.376us	1	1	100.00
		rv_timer_same_csr_outstanding	1.650s	18.403us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.470s	36.900us	1	1	100.00
		rv_timer_csr_rw	1.570s	81.950us	1	1	100.00
		rv_timer_csr_aliasing	1.640s	39.376us	1	1	100.00
		rv_timer_same_csr_outstanding	1.650s	18.403us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.630s	64.380us	1	1	100.00
		rv_timer_tl_intg_err	1.880s	56.775us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.880s	56.775us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	18.240s	3.080ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.490s	167.115us	1	1	100.00
		rv_timer_max	1.650s	16.048us	1	1	100.00
		TOTAL			19	19	100.00