SPI_DEVICE/1R1W Simulation Results

Tuesday May 13 2025 20:18:55 UTC

GitHub Revision: 81efe90

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	31.060s	3.129ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.800s	71.180us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.220s	83.891us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	25.090s	16.367ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.310s	320.619us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.930s	85.877us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.220s	83.891us	1	1	100.00
		spi_device_csr_aliasing	15.310s	320.619us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.680s	23.647us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.580s	255.661us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.860s	77.481us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.830s	5.186us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.740s	4.129us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.180s	209.922us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.180s	209.922us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.150s	1.615ms	1	1	100.00
		spi_device_tpm_sts_read	1.870s	332.764us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	18.150s	9.800ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	14.280s	28.667ms	1	1	100.00
		spi_device_flash_all	17.590s	15.175ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	16.880s	8.679ms	1	1	100.00
		spi_device_flash_all	17.590s	15.175ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	16.880s	8.679ms	1	1	100.00
		spi_device_flash_all	17.590s	15.175ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	17.590s	15.175ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	18.460s	5.204ms	1	1	100.00
		spi_device_flash_all	17.590s	15.175ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	18.460s	5.204ms	1	1	100.00
		spi_device_flash_all	17.590s	15.175ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	18.460s	5.204ms	1	1	100.00
		spi_device_flash_all	17.590s	15.175ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	18.460s	5.204ms	1	1	100.00
		spi_device_flash_all	17.590s	15.175ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	18.460s	5.204ms	1	1	100.00
		spi_device_flash_all	17.590s	15.175ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.250s	171.483us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	12.400s	666.523us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	12.400s	666.523us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	12.400s	666.523us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.310s	139.830us	1	1	100.00
		spi_device_read_buffer_direct	4.440s	1.941ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	12.400s	666.523us	1	1	100.00
		spi_device_flash_all	17.590s	15.175ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	17.590s	15.175ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	17.590s	15.175ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.120s	115.581us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.120s	115.581us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	31.060s	3.129ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.758m	332.283ms	1	1	100.00
V2	stress_all	spi_device_stress_all	11.679m	131.042ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.560s	39.300us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.830s	14.338us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.090s	103.120us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.090s	103.120us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.800s	71.180us	1	1	100.00
		spi_device_csr_rw	2.220s	83.891us	1	1	100.00
		spi_device_csr_aliasing	15.310s	320.619us	1	1	100.00
		spi_device_same_csr_outstanding	3.920s	212.760us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.800s	71.180us	1	1	100.00
		spi_device_csr_rw	2.220s	83.891us	1	1	100.00
		spi_device_csr_aliasing	15.310s	320.619us	1	1	100.00
		spi_device_same_csr_outstanding	3.920s	212.760us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.040s	262.797us	1	1	100.00
		spi_device_tl_intg_err	5.840s	478.934us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.840s	478.934us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	34.420s	31.131ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.27458232380298437123875248738659290591894288357491316711142094086188902254344
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4367713 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[32])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4367713 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4367713 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[928])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.9603350472882758695417748281440948764601343762681870401241442656406511285939
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1866843 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7316db [11100110001011011011011] vs 0x0 [0])
        UVM_ERROR @   1889843 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe8f28b [111010001111001010001011] vs 0x0 [0])
        UVM_ERROR @   1965843 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x76ebde [11101101110101111011110] vs 0x0 [0])
        UVM_ERROR @   2011843 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6ed25 [1101110110100100101] vs 0x0 [0])
        UVM_ERROR @   2085843 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcdd995 [110011011101100110010101] vs 0x0 [0])