SPI_DEVICE/2P Simulation Results

Tuesday May 13 2025 20:18:55 UTC

GitHub Revision: 81efe90

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 3.175m 231.195ms 1 1 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 2.040s 90.353us 1 1 100.00
V1 csr_rw spi_device_csr_rw 2.310s 68.567us 1 1 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 23.910s 2.375ms 1 1 100.00
V1 csr_aliasing spi_device_csr_aliasing 18.780s 13.274ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 2.980s 686.303us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.310s 68.567us 1 1 100.00
spi_device_csr_aliasing 18.780s 13.274ms 1 1 100.00
V1 mem_walk spi_device_mem_walk 1.550s 18.726us 1 1 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.120s 248.275us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 csb_read spi_device_csb_read 2.060s 16.457us 1 1 100.00
V2 mem_parity spi_device_mem_parity 2.060s 27.982us 1 1 100.00
V2 mem_cfg spi_device_ram_cfg 2.180s 26.450us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 1.980s 109.209us 1 1 100.00
V2 tpm_write spi_device_tpm_rw 1.980s 109.209us 1 1 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 8.690s 14.064ms 1 1 100.00
spi_device_tpm_sts_read 1.630s 88.134us 1 1 100.00
V2 tpm_fully_random_case spi_device_tpm_all 11.460s 5.352ms 1 1 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 7.670s 16.080ms 1 1 100.00
spi_device_flash_all 1.046m 12.309ms 1 1 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 4.470s 1.192ms 1 1 100.00
spi_device_flash_all 1.046m 12.309ms 1 1 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 4.470s 1.192ms 1 1 100.00
spi_device_flash_all 1.046m 12.309ms 1 1 100.00
V2 cmd_info_slots spi_device_flash_all 1.046m 12.309ms 1 1 100.00
V2 cmd_read_status spi_device_intercept 4.180s 156.936us 1 1 100.00
spi_device_flash_all 1.046m 12.309ms 1 1 100.00
V2 cmd_read_jedec spi_device_intercept 4.180s 156.936us 1 1 100.00
spi_device_flash_all 1.046m 12.309ms 1 1 100.00
V2 cmd_read_sfdp spi_device_intercept 4.180s 156.936us 1 1 100.00
spi_device_flash_all 1.046m 12.309ms 1 1 100.00
V2 cmd_fast_read spi_device_intercept 4.180s 156.936us 1 1 100.00
spi_device_flash_all 1.046m 12.309ms 1 1 100.00
V2 cmd_read_pipeline spi_device_intercept 4.180s 156.936us 1 1 100.00
spi_device_flash_all 1.046m 12.309ms 1 1 100.00
V2 flash_cmd_upload spi_device_upload 5.710s 11.240ms 1 1 100.00
V2 mailbox_command spi_device_mailbox 4.460s 3.627ms 1 1 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 4.460s 3.627ms 1 1 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 4.460s 3.627ms 1 1 100.00
V2 cmd_read_buffer spi_device_flash_mode 6.110s 267.284us 1 1 100.00
spi_device_read_buffer_direct 5.180s 7.435ms 1 1 100.00
V2 cmd_dummy_cycle spi_device_mailbox 4.460s 3.627ms 1 1 100.00
spi_device_flash_all 1.046m 12.309ms 1 1 100.00
V2 quad_spi spi_device_flash_all 1.046m 12.309ms 1 1 100.00
V2 dual_spi spi_device_flash_all 1.046m 12.309ms 1 1 100.00
V2 4b_3b_feature spi_device_cfg_cmd 12.300s 13.570ms 1 1 100.00
V2 write_enable_disable spi_device_cfg_cmd 12.300s 13.570ms 1 1 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 3.175m 231.195ms 1 1 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 4.598m 901.321ms 1 1 100.00
V2 stress_all spi_device_stress_all 1.306m 11.560ms 1 1 100.00
V2 alert_test spi_device_alert_test 1.580s 132.139us 1 1 100.00
V2 intr_test spi_device_intr_test 1.670s 23.552us 1 1 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 3.460s 59.551us 1 1 100.00
V2 tl_d_illegal_access spi_device_tl_errors 3.460s 59.551us 1 1 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 2.040s 90.353us 1 1 100.00
spi_device_csr_rw 2.310s 68.567us 1 1 100.00
spi_device_csr_aliasing 18.780s 13.274ms 1 1 100.00
spi_device_same_csr_outstanding 3.400s 140.694us 1 1 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 2.040s 90.353us 1 1 100.00
spi_device_csr_rw 2.310s 68.567us 1 1 100.00
spi_device_csr_aliasing 18.780s 13.274ms 1 1 100.00
spi_device_same_csr_outstanding 3.400s 140.694us 1 1 100.00
V2 TOTAL 22 22 100.00
V2S tl_intg_err spi_device_sec_cm 1.800s 124.574us 1 1 100.00
spi_device_tl_intg_err 6.570s 277.060us 1 1 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 6.570s 277.060us 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests spi_device_flash_mode_ignore_cmds 1.323m 56.984ms 1 1 100.00
TOTAL 33 33 100.00