SPI_HOST Simulation Results

Tuesday May 13 2025 20:18:55 UTC

GitHub Revision: 81efe90

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	36.000s	1.094ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	50.018us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	39.546us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	247.674us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	23.140us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	21.347us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	39.546us	1	1	100.00
		spi_host_csr_aliasing	4.000s	23.140us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	32.567us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	18.261us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	31.759us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	6.000s	174.144us	1	1	100.00
		spi_host_error_cmd	4.000s	46.372us	1	1	100.00
		spi_host_event	14.000s	405.635us	1	1	100.00
V2	clock_rate	spi_host_speed	5.000s	84.336us	1	1	100.00
V2	speed	spi_host_speed	5.000s	84.336us	1	1	100.00
V2	chip_select_timing	spi_host_speed	5.000s	84.336us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	1.483m	11.831ms	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	29.208us	1	1	100.00
V2	cpol_cpha	spi_host_speed	5.000s	84.336us	1	1	100.00
V2	full_cycle	spi_host_speed	5.000s	84.336us	1	1	100.00
V2	duplex	spi_host_smoke	36.000s	1.094ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	36.000s	1.094ms	1	1	100.00
V2	stress_all	spi_host_stress_all	22.000s	2.080ms	1	1	100.00
V2	spien	spi_host_spien	5.000s	164.286us	1	1	100.00
V2	stall	spi_host_status_stall	20.000s	4.496ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	95.596us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	6.000s	174.144us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	33.882us	1	1	100.00
V2	intr_test	spi_host_intr_test	3.000s	20.992us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	114.391us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	114.391us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	50.018us	1	1	100.00
		spi_host_csr_rw	3.000s	39.546us	1	1	100.00
		spi_host_csr_aliasing	4.000s	23.140us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	49.667us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	50.018us	1	1	100.00
		spi_host_csr_rw	3.000s	39.546us	1	1	100.00
		spi_host_csr_aliasing	4.000s	23.140us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	49.667us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	80.065us	1	1	100.00
		spi_host_sec_cm	3.000s	123.276us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	80.065us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	1.400m	200.000ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.5300841374598753631256273674159407926641226722284429907941406997460484871052
      Line 136, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---