SRAM_CTRL/MAIN Simulation Results

Tuesday May 13 2025 20:18:55 UTC

GitHub Revision: 81efe90

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	46.950s	469.251us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.590s	18.544us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.540s	39.171us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.100s	557.751us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.600s	59.385us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.420s	352.122us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.540s	39.171us	1	1	100.00
		sram_ctrl_csr_aliasing	1.600s	59.385us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.730m	2.633ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.081m	13.610ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.600m	61.097ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.766m	4.496ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	11.038m	205.717ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.649m	11.299ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	13.270s	6.439ms	1	1	100.00
V2	executable	sram_ctrl_executable	10.396m	119.802ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	6.180s	2.882ms	1	1	100.00
		sram_ctrl_partial_access_b2b	6.210m	64.911ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	52.280s	987.756us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	13.010s	2.721ms	1	1	100.00
		sram_ctrl_throughput_w_readback	25.120s	869.865us	1	1	100.00
V2	regwen	sram_ctrl_regwen	2.188m	5.924ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.610s	696.497us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	45.365m	110.037ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.590s	34.168us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.100s	1.064ms	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.100s	1.064ms	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.590s	18.544us	1	1	100.00
		sram_ctrl_csr_rw	1.540s	39.171us	1	1	100.00
		sram_ctrl_csr_aliasing	1.600s	59.385us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.540s	52.990us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.590s	18.544us	1	1	100.00
		sram_ctrl_csr_rw	1.540s	39.171us	1	1	100.00
		sram_ctrl_csr_aliasing	1.600s	59.385us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.540s	52.990us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	17.870s	23.184ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.550s	15.235us	0	1	0.00
		sram_ctrl_tl_intg_err	2.920s	742.028us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.550s	15.235us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.920s	742.028us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	2.188m	5.924ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	2.188m	5.924ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.540s	39.171us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	10.396m	119.802ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	10.396m	119.802ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	10.396m	119.802ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	13.270s	6.439ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.660s	699.506us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	17.870s	23.184ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.770s	1.349ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	46.950s	469.251us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	46.950s	469.251us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	10.396m	119.802ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.550s	15.235us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	13.270s	6.439ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.550s	15.235us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.550s	15.235us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	46.950s	469.251us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.550s	15.235us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	44.360s	1.043ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.110789977840997017844094150195530720508906312580598711804076237401788608935096
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  15235234 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  15235234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---