SRAM_CTRL/RET Simulation Results

Tuesday May 13 2025 20:18:55 UTC

GitHub Revision: 81efe90

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.000m	2.307ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.640s	32.509us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.610s	114.621us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.640s	356.197us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.490s	79.307us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.750s	25.342us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.610s	114.621us	1	1	100.00
		sram_ctrl_csr_aliasing	1.490s	79.307us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.980s	1.982ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.290s	217.683us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	4.356m	19.173ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.575m	6.151ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	47.380s	1.017ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	9.321m	17.640ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	8.960s	584.576us	1	1	100.00
V2	executable	sram_ctrl_executable	4.629m	11.567ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	9.100s	254.778us	1	1	100.00
		sram_ctrl_partial_access_b2b	6.299m	90.705ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	3.460s	52.253us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	8.510s	550.054us	1	1	100.00
		sram_ctrl_throughput_w_readback	45.340s	1.070ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	2.766m	6.829ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.860s	78.123us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	17.973m	44.450ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.610s	15.198us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.530s	43.992us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.530s	43.992us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.640s	32.509us	1	1	100.00
		sram_ctrl_csr_rw	1.610s	114.621us	1	1	100.00
		sram_ctrl_csr_aliasing	1.490s	79.307us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.530s	13.881us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.640s	32.509us	1	1	100.00
		sram_ctrl_csr_rw	1.610s	114.621us	1	1	100.00
		sram_ctrl_csr_aliasing	1.490s	79.307us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.530s	13.881us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.800s	453.255us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.060s	12.255us	0	1	0.00
		sram_ctrl_tl_intg_err	2.120s	532.074us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.060s	12.255us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.120s	532.074us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	2.766m	6.829ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	2.766m	6.829ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.610s	114.621us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.629m	11.567ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.629m	11.567ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.629m	11.567ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	8.960s	584.576us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.040s	53.689us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.800s	453.255us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.080s	31.739us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.000m	2.307ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.000m	2.307ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.629m	11.567ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.060s	12.255us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	8.960s	584.576us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.060s	12.255us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.060s	12.255us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.000m	2.307ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.060s	12.255us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	42.690s	1.085ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.54073210890228570147300767502668449113334566439265153282149397774237428467804
      Line 97, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  12254574 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  12254574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---