SYSRST_CTRL Simulation Results

Tuesday May 13 2025 20:18:55 UTC

GitHub Revision: `81efe90`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	2.840s	2.138ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	7.010s	2.455ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	7.500s	2.255ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	2.830s	2.587ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	9.740s	4.035ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	2.870s	2.072ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	42.800s	73.010ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	6.800s	2.587ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	3.850s	2.093ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	2.870s	2.072ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	6.800s	2.587ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	45.800s	104.784ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	2.382m	74.497ms	0	1	0.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	49.610s	50.905ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	3.890s	2.750ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.120s	2.509ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	5.730s	2.211ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	2.680s	2.606ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	2.930s	2.626ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	5.690s	3.881ms	0	1	0.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.103m	35.303ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	22.510s	8.973ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	3.330s	2.024ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	3.300s	2.047ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	7.400s	2.121ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	7.400s	2.121ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	9.740s	4.035ms	1	1	100.00
		sysrst_ctrl_csr_rw	2.870s	2.072ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	6.800s	2.587ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	5.320s	5.479ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	9.740s	4.035ms	1	1	100.00
		sysrst_ctrl_csr_rw	2.870s	2.072ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	6.800s	2.587ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	5.320s	5.479ms	1	1	100.00
V2		TOTAL			13	15	86.67
V2S	tl_intg_err	sysrst_ctrl_sec_cm	11.010s	22.134ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	23.530s	42.539ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	23.530s	42.539ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	7.620s	3.243ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:

Test sysrst_ctrl_ultra_low_pwr has 1 failures.

0.sysrst_ctrl_ultra_low_pwr.4763070290108945032575028624606150353016784132167781166216005689026816439684
Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 3880900700 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 3880932277 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 3880932277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(9) vs exp(4) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

0.sysrst_ctrl_combo_detect_with_pre_cond.18459286772392403894279538004677852299282855037149906830810103437776979430324
Line 389, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 13955878307 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(9) vs exp(4) +/-4
  UVM_INFO @ 13960878307 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0
  UVM_INFO @ 14185878307 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 14205878307 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 16206009959 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3