UART Simulation Results

Tuesday May 13 2025 20:18:55 UTC

GitHub Revision: 81efe90

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.760s	306.699us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.650s	20.636us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.600s	39.257us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.930s	891.985us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.640s	18.056us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.730s	31.636us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.600s	39.257us	1	1	100.00
		uart_csr_aliasing	1.640s	18.056us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.869m	83.982ms	1	1	100.00
V2	parity	uart_smoke	1.760s	306.699us	1	1	100.00
		uart_tx_rx	1.869m	83.982ms	1	1	100.00
V2	parity_error	uart_intr	6.590s	31.132ms	1	1	100.00
		uart_rx_parity_err	54.670s	56.447ms	1	1	100.00
V2	watermark	uart_tx_rx	1.869m	83.982ms	1	1	100.00
		uart_intr	6.590s	31.132ms	1	1	100.00
V2	fifo_full	uart_fifo_full	2.322m	115.534ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	40.570s	156.970ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	16.580s	183.386ms	1	1	100.00
V2	rx_frame_err	uart_intr	6.590s	31.132ms	1	1	100.00
V2	rx_break_err	uart_intr	6.590s	31.132ms	1	1	100.00
V2	rx_timeout	uart_intr	6.590s	31.132ms	1	1	100.00
V2	perf	uart_perf	8.120m	15.171ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.650s	1.527ms	1	1	100.00
V2	line_loopback	uart_loopback	2.650s	1.527ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	54.550s	49.083ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	16.230s	49.936ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	8.180s	8.383ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	11.360s	7.055ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.661m	72.970ms	1	1	100.00
V2	stress_all	uart_stress_all	32.130s	141.889ms	1	1	100.00
V2	alert_test	uart_alert_test	1.580s	12.815us	1	1	100.00
V2	intr_test	uart_intr_test	1.600s	11.586us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.530s	149.539us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.530s	149.539us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.650s	20.636us	1	1	100.00
		uart_csr_rw	1.600s	39.257us	1	1	100.00
		uart_csr_aliasing	1.640s	18.056us	1	1	100.00
		uart_same_csr_outstanding	1.580s	38.899us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.650s	20.636us	1	1	100.00
		uart_csr_rw	1.600s	39.257us	1	1	100.00
		uart_csr_aliasing	1.640s	18.056us	1	1	100.00
		uart_same_csr_outstanding	1.580s	38.899us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.720s	150.414us	1	1	100.00
		uart_tl_intg_err	2.050s	161.810us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.050s	161.810us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	46.390s	4.491ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00