CHIP Simulation Results

Tuesday May 13 2025 20:18:55 UTC

GitHub Revision: `81efe90`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.887m	3.008ms	1	1	100.00
		chip_sw_example_rom	1.089m	2.086ms	1	1	100.00
		chip_sw_example_manufacturer	2.168m	2.706ms	1	1	100.00
		chip_sw_example_concurrency	2.379m	2.719ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.691m	7.732ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.288m	3.852ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	7.744m	8.541ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.011h	34.131ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	8.138m	8.914ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.011h	34.131ms	1	1	100.00
		chip_csr_rw	3.288m	3.852ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.440s	213.766us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.747m	3.724ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.747m	3.724ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.747m	3.724ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.694m	4.892ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.694m	4.892ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.817m	4.043ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.664m	4.113ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.540m	3.644ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	15.189m	7.388ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	5.522m	4.125ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	11.118m	8.787ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	2.493m	4.918ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.493m	4.918ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.731m	3.015ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	5.399m	5.010ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.632m	3.027ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	2.974m	3.556ms	1	1	100.00
		chip_tap_straps_testunlock0	1.922m	3.144ms	1	1	100.00
		chip_tap_straps_rma	7.692m	8.361ms	1	1	100.00
		chip_tap_straps_prod	1.666m	2.675ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.911m	3.010ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.234m	7.969ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.296m	4.727ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.296m	4.727ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.395m	7.816ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	24.427m	15.738ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.280m	4.051ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.610m	5.703ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.431m	18.191ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.975m	3.698ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.384m	6.254ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.626m	2.925ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	8.675m	7.454ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.228m	3.418ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.488m	3.982ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.208m	2.814ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.386m	3.598ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	8.912m	7.225ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.420m	5.799ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	3.159m	2.397ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.420m	5.799ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.286m	2.498ms	1	1	100.00
		chip_sw_aes_smoketest	2.924m	2.958ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.169m	3.841ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.901m	2.675ms	1	1	100.00
		chip_sw_csrng_smoketest	3.149m	2.889ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.164m	3.670ms	1	1	100.00
		chip_sw_gpio_smoketest	2.600m	2.662ms	1	1	100.00
		chip_sw_hmac_smoketest	3.019m	2.839ms	1	1	100.00
		chip_sw_kmac_smoketest	3.619m	2.988ms	1	1	100.00
		chip_sw_otbn_smoketest	15.865m	8.918ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.777m	6.049ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.036m	5.522ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.854m	2.516ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.088m	3.012ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.805m	2.706ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.126m	2.333ms	1	1	100.00
		chip_sw_uart_smoketest	2.465m	2.976ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.966m	2.181ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.251m	4.369ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.066h	60.136ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	39.564m	14.866ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.855m	6.218ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.647m	3.079ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.857m	3.429ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.761h	55.006ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.898h	56.753ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	45.780s	2.818ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	45.780s	2.818ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.011h	34.131ms	1	1	100.00
		chip_same_csr_outstanding	34.881m	28.265ms	1	1	100.00
		chip_csr_hw_reset	3.691m	7.732ms	1	1	100.00
		chip_csr_rw	3.288m	3.852ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.011h	34.131ms	1	1	100.00
		chip_same_csr_outstanding	34.881m	28.265ms	1	1	100.00
		chip_csr_hw_reset	3.691m	7.732ms	1	1	100.00
		chip_csr_rw	3.288m	3.852ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	12.730s	536.715us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.850s	38.041us	1	1	100.00
		xbar_smoke_large_delays	42.500s	6.532ms	1	1	100.00
		xbar_smoke_slow_rsp	33.320s	3.872ms	1	1	100.00
		xbar_random_zero_delays	19.890s	392.223us	1	1	100.00
		xbar_random_large_delays	34.480s	5.412ms	1	1	100.00
		xbar_random_slow_rsp	4.585m	33.563ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	11.710s	357.805us	1	1	100.00
		xbar_error_and_unmapped_addr	14.190s	603.745us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	39.400s	1.932ms	1	1	100.00
		xbar_error_and_unmapped_addr	14.190s	603.745us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	32.330s	1.353ms	1	1	100.00
		xbar_access_same_device_slow_rsp	4.601m	33.402ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	27.890s	1.562ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.262m	3.874ms	1	1	100.00
		xbar_stress_all_with_error	43.300s	2.620ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	6.479m	12.759ms	1	1	100.00
		xbar_stress_all_with_reset_error	50.070s	195.838us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	39.564m	14.866ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	34.307m	25.262ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	38.430m	14.331ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	32.843m	11.463ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	40.093m	15.432ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	41.606m	16.060ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	41.262m	15.534ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	40.200m	15.369ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	27.840s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	27.280s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	31.580s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	29.060s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	32.000s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	27.910s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	28.040s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	26.640s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	26.930s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	27.590s	10.260us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	29.450s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	27.260s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	25.900s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	28.800s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	25.530s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	27.840s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	27.100s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	26.900s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	25.350s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	26.230s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	26.620s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	26.260s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	26.990s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	27.670s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	28.280s	10.320us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	31.333m	11.891ms	1	1	100.00
		rom_e2e_asm_init_dev	37.852m	15.867ms	1	1	100.00
		rom_e2e_asm_init_prod	37.315m	15.822ms	1	1	100.00
		rom_e2e_asm_init_prod_end	38.744m	15.523ms	1	1	100.00
		rom_e2e_asm_init_rma	35.718m	15.260ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	36.338m	14.768ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	36.209m	14.582ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	37.372m	14.793ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	36.568m	16.327ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	52.284m	34.630ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	52.284m	34.630ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.873m	3.211ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.975m	3.698ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.144m	3.472ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.151m	2.838ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	10.033m	7.486ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.417m	2.918ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	6.136m	5.133ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.999m	5.819ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.718m	5.828ms	1	1	100.00
		chip_plic_all_irqs_10	4.479m	4.286ms	1	1	100.00
		chip_plic_all_irqs_20	6.224m	4.315ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.814m	3.437ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	17.520m	11.278ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.475m	3.955ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.374m	2.398ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.844m	11.934ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.479m	5.630ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	15.347m	7.267ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	11.963m	7.939ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.269h	255.651ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.048m	4.096ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.777m	6.049ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.048m	4.096ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.346m	11.031ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.346m	11.031ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.734m	6.608ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.400m	5.235ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.739m	5.738ms	1	1	100.00
		chip_sw_aes_idle	2.151m	2.838ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.772m	2.790ms	1	1	100.00
		chip_sw_kmac_idle	2.308m	3.334ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.188m	4.795ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.815m	5.534ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.398m	4.565ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	5.261m	3.828ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	12.571m	12.352ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.299m	4.331ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.950m	5.385ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.037m	3.649ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.742m	4.951ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.078m	3.448ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.691m	4.644ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.395m	7.816ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	4.644m	5.627ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.037m	3.649ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.742m	4.951ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.280m	4.051ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.610m	5.703ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.431m	18.191ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.975m	3.698ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.384m	6.254ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.626m	2.925ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	8.675m	7.454ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.228m	3.418ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.488m	3.982ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.208m	2.814ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.693m	2.227ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.724m	3.885ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.223m	7.048ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	50.324m	24.176ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.468m	3.708ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.895m	3.401ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.765m	7.624ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.691m	2.694ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.174m	4.870ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	18.668m	20.614ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	35.377m	20.412ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.395m	7.816ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.449m	4.221ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.304m	3.283ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.999m	5.819ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	10.479m	5.630ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	17.512m	8.705ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	3.149m	3.033ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.498m	6.390ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.118m	2.786ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	32.104m	13.993ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.534m	3.510ms	1	1	100.00
		chip_sw_edn_entropy_reqs	12.367m	6.445ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.534m	3.510ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	17.512m	8.705ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.443m	2.758ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	14.909m	15.388ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.300m	4.966ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.610m	5.703ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.421m	3.576ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.280m	4.051ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	51.511m	44.373ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	14.909m	15.388ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.288m	3.379ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	19.103m	10.741ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.234m	4.258ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	51.511m	44.373ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.234m	4.258ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.234m	4.258ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.234m	4.258ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.234m	4.258ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.999m	5.819ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.871m	7.432ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	9.149m	4.631ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.458m	5.907ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.458m	5.907ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.488m	2.826ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.626m	2.925ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.772m	2.790ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.263m	3.490ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	16.184m	7.767ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	7.019m	4.903ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.786m	5.046ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.754m	5.132ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.202m	3.841ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	19.103m	10.741ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	8.675m	7.454ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	22.779m	11.437ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	10.033m	7.486ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	45.203m	15.517ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.228m	3.403ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.367m	3.603ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.228m	3.418ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	19.103m	10.741ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.096m	6.628ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.885m	3.077ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	15.277m	7.279ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.308m	3.334ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	6.136m	5.133ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	2.974m	3.556ms	1	1	100.00
		chip_tap_straps_rma	7.692m	8.361ms	1	1	100.00
		chip_tap_straps_prod	1.666m	2.675ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.049m	3.120ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.096m	6.628ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.096m	6.628ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.096m	6.628ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	11.806m	7.498ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.234m	4.258ms	1	1	100.00
		chip_sw_flash_rma_unlocked	51.511m	44.373ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.938m	2.962ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.708m	7.521ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.065m	7.524ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.709m	6.306ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.096m	6.628ms	1	1	100.00
		chip_sw_keymgr_key_derivation	19.103m	10.741ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.512m	9.665ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	7.244m	7.175ms	1	1	100.00
		chip_prim_tl_access	2.871m	7.432ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	4.644m	5.627ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.299m	4.331ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.950m	5.385ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.037m	3.649ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.742m	4.951ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.078m	3.448ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.691m	4.644ms	1	1	100.00
		chip_tap_straps_dev	2.974m	3.556ms	1	1	100.00
		chip_tap_straps_rma	7.692m	8.361ms	1	1	100.00
		chip_tap_straps_prod	1.666m	2.675ms	1	1	100.00
		chip_rv_dm_lc_disabled	8.334m	18.142ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.334m	3.269ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.557m	2.830ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.690m	3.433ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.427m	3.853ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	23.334m	33.683ms	1	1	100.00
		chip_rv_dm_lc_disabled	8.334m	18.142ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.085h	47.409ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	57.351m	50.006ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.147m	8.371ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	59.710m	49.153ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	23.334m	33.683ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.383m	2.794ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.198m	2.362ms	1	1	100.00
		rom_volatile_raw_unlock	1.121m	2.433ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	53.059m	16.239ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.431m	18.191ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.739m	5.738ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.739m	5.738ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.739m	5.738ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	3.824m	3.734ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.096m	6.628ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	14.909m	15.388ms	1	1	100.00
		chip_sw_otbn_mem_scramble	3.824m	3.734ms	1	1	100.00
		chip_sw_keymgr_key_derivation	19.103m	10.741ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.767m	3.493ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.144m	2.685ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	14.909m	15.388ms	1	1	100.00
		chip_sw_otbn_mem_scramble	3.824m	3.734ms	1	1	100.00
		chip_sw_keymgr_key_derivation	19.103m	10.741ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.767m	3.493ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.144m	2.685ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.096m	6.628ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	3.745m	4.650ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.049m	3.120ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.938m	2.962ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.708m	7.521ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.065m	7.524ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.709m	6.306ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.096m	6.628ms	1	1	100.00
		chip_prim_tl_access	2.871m	7.432ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.871m	7.432ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	15.060m	8.649ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.141m	9.020ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	16.090m	25.005ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.775m	7.180ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	7.043m	9.457ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.947m	6.529ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	16.881m	23.144ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	13.274m	17.469ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	9.346m	11.031ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	10.467m	8.776ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.823m	5.405ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.141m	9.020ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.898m	4.815ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	26.836m	32.431ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.552m	7.209ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.454m	4.425ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	19.682m	23.850ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.032m	7.274ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	13.079m	10.619ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	20.830m	29.751ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.442m	3.242ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.999m	5.819ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.512m	9.665ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.512m	9.665ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	13.079m	10.619ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	19.682m	23.850ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.823m	5.405ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.777m	6.049ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.715m	4.514ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.143m	4.391ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.888m	4.695ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	17.520m	11.278ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.760m	2.948ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.999m	5.819ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	15.347m	7.267ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.136m	5.254ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.966m	4.478ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.840m	3.097ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.144m	2.685ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.143m	4.391ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.143m	4.391ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	18.850m	18.812ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.758m	13.452ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.715m	4.514ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.149m	5.322ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	5.614m	6.978ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	7.692m	8.361ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	8.334m	18.142ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.718m	5.828ms	1	1	100.00
		chip_plic_all_irqs_10	4.479m	4.286ms	1	1	100.00
		chip_plic_all_irqs_20	6.224m	4.315ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.534m	3.005ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	3.032m	2.767ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	39.564m	14.866ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.920m	6.713ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.722m	2.773ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.851m	3.501ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.897m	2.699ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.767m	3.493ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.488m	3.982ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	6.499m	7.826ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.838m	8.248ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	7.244m	7.175ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.999m	5.819ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.296m	4.727ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.032m	7.274ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	17.027m	23.076ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	3.297m	3.011ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.762m	3.760ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.032m	4.360ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	17.027m	23.076ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	17.027m	23.076ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	13.291m	12.074ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	13.291m	12.074ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.238m	5.587ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	52.284m	34.630ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.686m	2.809ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.794m	3.045ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.310m	3.605ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.174m	3.606ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.023m	8.005ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.288h	31.775ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	25.574m	12.459ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.328m	3.085ms	1	1	100.00
V2		TOTAL			239	275	86.91
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.928m	2.928ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.697m	3.058ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.427h	71.801ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	5.626m	3.689ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	17.775m	10.937ms	1	1	100.00
		rom_e2e_jtag_debug_dev	19.012m	12.062ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.068m	11.197ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.757m	2.996ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.736m	3.389ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.568m	3.735ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	13.685s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.746m	5.463ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.736m	2.785ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	10.859m	4.749ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	13.696m	6.569ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.255m	2.217ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.033m	4.379ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.608m	3.500ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.093m	4.880ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.389m	4.561ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.145m	5.273ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	13.079m	10.619ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	17.775m	10.937ms	1	1	100.00
		rom_e2e_jtag_debug_dev	19.012m	12.062ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.068m	11.197ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.820m	5.324ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.999m	5.819ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.384h	38.586ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.384h	38.586ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.231m	3.331ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.694m	4.892ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	46.176m	18.694ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.736m	2.821ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	4.929m	4.533ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.959m	2.653ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.657m	3.044ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.222m	3.995ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.908s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.897m	2.457ms	1	1	100.00
		TOTAL			285	325	87.69

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.20706150593531559593010857205164169170608426504614024988057046237266929442279
    Line 616, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.9618891675858951753509764948051342146612602265602592187247287863558515558644
    Line 649, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.18315548910457669092335558413624703454031038394845651580273326052161805475343
    Line 783, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.862559615485332411358658109220973349255963684264011283162194759185080972124
    Line 803, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.114800975983384666510429788623352957494122682706430669041491379315121762908816
    Line 669, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.87971174132387420080788875079686119627323609411143081916154345357172345174741
    Line 647, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.113504800083444498274466752791398557277052044027000995817831606751142647102152
    Line 661, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.102023069602788176474225689580144541367547561685211133648186218250487305322859
    Line 693, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.34520862473482785498307689355069652612102257505504356257886938319054043979814
    Line 626, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.110776922778409909686922490322057417723767615931853062406608694371137596432089
    Line 647, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.97693564658305493139512156246003050416095214534612317878710283023504381589647
    Line 686, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.33481841319707199581947122875316531803908429711167591870473296472146949347370
    Line 696, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.90547224944882211344660382130625829087308821272902331784317554440734269776440
    Line 673, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.63806663220036901807694419041747783628063676302898098337884650914275094171306
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.144s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.36214283364210392960390888747647616535864825884172297440212216085502285511675
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 3.575s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.31582943064038109562923771034573025052643361114788875461713286807244416804268
    Line 800, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.42544988245963864988074714515709173802798810006714919132546306607200258744359
    Line 641, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.12287391345993541996851728557749896599348488679938280410887070668074643756696
    Line 758, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.25804823397745491102688816631813829296282989024704808708637834704699475115145
    Line 628, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.39647257251842937470785021246220114200451053759803044369770478987769842604894
    Line 420, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2773.203574 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2773.203574 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@95381) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.100893346357946585216392392447922214549297113199329423961286445089580256960374
Line 449, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4390.656786 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@95381) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4390.656786 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.49382421193087780667776495825843898050452850339827950093589182231813263827307
    Line 422, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 12073.914562 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 12073.914562 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.13680045455588173626001524007330226420335959245608883423700251377928407326035
    Line 427, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34629.740179 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34629.740179 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.112398493308726660756766372410443376261695920992955633620040800437084199459384
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2918.240762 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2918.240762 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.8055003807810224806359545822703654440639523377396940016269716735559315309089
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2398.007124 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2398.007124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.99627299157228561152544438612505694818106481652553627174816213880116678359680
    Line 407, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 3033.194524 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 3033.194524 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33379) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.3855586480969127965631502862544841669232038757241469732192661501499583960458
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2817.534300 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33379) { a_addr: 'h105c8  a_data: 'hbf8c08a5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2f  a_opcode: 'h4  a_user: 'h19e78  d_param: 'h0  d_source: 'h2f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2817.534300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.73582334091318828711314424059522421064501502525661631479675671651721563224649
    Line 429, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 3058.213100 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 3058.213100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.20741897154627313009448747659602033092751198579968832156918229546431643610869
    Line 421, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3079.243000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3079.243000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.22731345759274294618058789605151937773924408356382614147781082938648140064575
    Line 429, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3429.242000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3429.242000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.40573216268337289283566599901336628233362700267096016623686750929646251828855
    Line 436, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 15737.610951 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 15737.610951 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.96986098341703794468142515729425304283011510260589192810002432910392627531627
    Line 464, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3688.798298 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3688.798298 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.96150544590419904504959871682809931744886807741872707493187292081097005527875
    Line 722, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.34004306890584398984532604647401660182846278193840270712373297298858200253702
    Line 634, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```