ADC_CTRL Simulation Results

Wednesday May 14 2025 18:36:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	12.060s	5.629ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.040s	1.054ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.340s	509.525us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	19.140s	53.712ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.820s	879.877us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.090s	456.430us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.340s	509.525us	1	1	100.00
		adc_ctrl_csr_aliasing	3.820s	879.877us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	12.603m	493.771ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	6.312m	486.144ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	3.256m	492.911ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	2.545m	326.975ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	2.394m	182.481ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	8.986m	604.399ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	16.215m	600.000ms	0	1	0.00
V2	clock_gating	adc_ctrl_clock_gating	3.599m	604.046ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	8.130s	2.741ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.006m	42.773ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	22.250s	98.426ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	2.214m	384.827ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.270s	427.229us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.850s	319.166us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.770s	853.866us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.770s	853.866us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.040s	1.054ms	1	1	100.00
		adc_ctrl_csr_rw	2.340s	509.525us	1	1	100.00
		adc_ctrl_csr_aliasing	3.820s	879.877us	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.450s	3.149ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.040s	1.054ms	1	1	100.00
		adc_ctrl_csr_rw	2.340s	509.525us	1	1	100.00
		adc_ctrl_csr_aliasing	3.820s	879.877us	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.450s	3.149ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	5.280s	3.929ms	1	1	100.00
		adc_ctrl_tl_intg_err	6.620s	8.291ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	6.620s	8.291ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	4.130s	5.671ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 0.adc_ctrl_filters_both.36067480634644541183800158571543094836599621192539616121457436031939185583646
      Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---