AES/UNMASKED Simulation Results

Wednesday May 14 2025 18:36:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	60.427us	1	1	100.00
V1	smoke	aes_smoke	6.000s	68.480us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	90.467us	1	1	100.00
V1	csr_rw	aes_csr_rw	4.000s	104.906us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	6.000s	121.578us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	68.458us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	123.898us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	104.906us	1	1	100.00
		aes_csr_aliasing	5.000s	68.458us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	6.000s	68.480us	1	1	100.00
		aes_config_error	5.000s	369.771us	1	1	100.00
		aes_stress	5.000s	67.777us	1	1	100.00
V2	key_length	aes_smoke	6.000s	68.480us	1	1	100.00
		aes_config_error	5.000s	369.771us	1	1	100.00
		aes_stress	5.000s	67.777us	1	1	100.00
V2	back2back	aes_stress	5.000s	67.777us	1	1	100.00
		aes_b2b	6.000s	139.691us	1	1	100.00
V2	backpressure	aes_stress	5.000s	67.777us	1	1	100.00
V2	multi_message	aes_smoke	6.000s	68.480us	1	1	100.00
		aes_config_error	5.000s	369.771us	1	1	100.00
		aes_stress	5.000s	67.777us	1	1	100.00
		aes_alert_reset	6.000s	175.703us	1	1	100.00
V2	failure_test	aes_man_cfg_err	4.000s	98.849us	1	1	100.00
		aes_config_error	5.000s	369.771us	1	1	100.00
		aes_alert_reset	6.000s	175.703us	1	1	100.00
V2	trigger_clear_test	aes_clear	6.000s	171.233us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	581.608us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	175.703us	1	1	100.00
V2	stress	aes_stress	5.000s	67.777us	1	1	100.00
V2	sideload	aes_stress	5.000s	67.777us	1	1	100.00
		aes_sideload	5.000s	91.967us	1	1	100.00
V2	deinitialization	aes_deinit	6.000s	265.492us	1	1	100.00
V2	stress_all	aes_stress_all	20.000s	935.709us	1	1	100.00
V2	alert_test	aes_alert_test	4.000s	64.109us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	643.644us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	643.644us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	90.467us	1	1	100.00
		aes_csr_rw	4.000s	104.906us	1	1	100.00
		aes_csr_aliasing	5.000s	68.458us	1	1	100.00
		aes_same_csr_outstanding	5.000s	321.039us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	90.467us	1	1	100.00
		aes_csr_rw	4.000s	104.906us	1	1	100.00
		aes_csr_aliasing	5.000s	68.458us	1	1	100.00
		aes_same_csr_outstanding	5.000s	321.039us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	5.000s	72.318us	1	1	100.00
V2S	fault_inject	aes_fi	5.000s	97.031us	1	1	100.00
		aes_control_fi	5.000s	111.161us	1	1	100.00
		aes_cipher_fi	4.000s	99.967us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	75.752us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	75.752us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	75.752us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	75.752us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	203.358us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	5.000s	1.089ms	1	1	100.00
		aes_tl_intg_err	6.000s	777.466us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	777.466us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	175.703us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	75.752us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	68.480us	1	1	100.00
		aes_stress	5.000s	67.777us	1	1	100.00
		aes_alert_reset	6.000s	175.703us	1	1	100.00
		aes_core_fi	5.000s	296.666us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	75.752us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	178.016us	1	1	100.00
		aes_stress	5.000s	67.777us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	67.777us	1	1	100.00
		aes_sideload	5.000s	91.967us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	178.016us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	178.016us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	178.016us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	178.016us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	178.016us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	67.777us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	67.777us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	97.031us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	97.031us	1	1	100.00
		aes_control_fi	5.000s	111.161us	1	1	100.00
		aes_cipher_fi	4.000s	99.967us	1	1	100.00
		aes_ctr_fi	4.000s	51.903us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	97.031us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	97.031us	1	1	100.00
		aes_control_fi	5.000s	111.161us	1	1	100.00
		aes_cipher_fi	4.000s	99.967us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	4.000s	99.967us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	97.031us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	97.031us	1	1	100.00
		aes_control_fi	5.000s	111.161us	1	1	100.00
		aes_ctr_fi	4.000s	51.903us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	97.031us	1	1	100.00
		aes_control_fi	5.000s	111.161us	1	1	100.00
		aes_cipher_fi	4.000s	99.967us	1	1	100.00
		aes_ctr_fi	4.000s	51.903us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	175.703us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	97.031us	1	1	100.00
		aes_control_fi	5.000s	111.161us	1	1	100.00
		aes_cipher_fi	4.000s	99.967us	1	1	100.00
		aes_ctr_fi	4.000s	51.903us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	97.031us	1	1	100.00
		aes_control_fi	5.000s	111.161us	1	1	100.00
		aes_cipher_fi	4.000s	99.967us	1	1	100.00
		aes_ctr_fi	4.000s	51.903us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	97.031us	1	1	100.00
		aes_control_fi	5.000s	111.161us	1	1	100.00
		aes_ctr_fi	4.000s	51.903us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	97.031us	1	1	100.00
		aes_control_fi	5.000s	111.161us	1	1	100.00
		aes_cipher_fi	4.000s	99.967us	1	1	100.00
V2S		TOTAL			11	11	100.00
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.000s	54.165us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			31	32	96.88

Failure Buckets

• UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.101240878979214526781021681763596306235683014839884129896789650289212430008224
      Line 144, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @  54164857 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @  54164857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---