EDN Simulation Results

Wednesday May 14 2025 18:36:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.780s 27.695us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.700s 32.347us 1 1 100.00
V1 csr_rw edn_csr_rw 1.890s 48.555us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.190s 176.376us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.980s 79.618us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.020s 95.356us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.890s 48.555us 1 1 100.00
edn_csr_aliasing 1.980s 79.618us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 2.000s 45.765us 1 1 100.00
V2 csrng_commands edn_genbits 2.000s 45.765us 1 1 100.00
V2 genbits edn_genbits 2.000s 45.765us 1 1 100.00
V2 interrupts edn_intr 1.760s 19.866us 1 1 100.00
V2 alerts edn_alert 1.800s 83.439us 1 1 100.00
V2 errs edn_err 1.880s 20.389us 1 1 100.00
V2 disable edn_disable 1.650s 34.838us 1 1 100.00
edn_disable_auto_req_mode 1.850s 225.084us 1 1 100.00
V2 stress_all edn_stress_all 3.480s 152.202us 1 1 100.00
V2 intr_test edn_intr_test 1.690s 22.842us 1 1 100.00
V2 alert_test edn_alert_test 1.790s 26.967us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.190s 46.222us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 3.190s 46.222us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.700s 32.347us 1 1 100.00
edn_csr_rw 1.890s 48.555us 1 1 100.00
edn_csr_aliasing 1.980s 79.618us 1 1 100.00
edn_same_csr_outstanding 2.060s 62.070us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.700s 32.347us 1 1 100.00
edn_csr_rw 1.890s 48.555us 1 1 100.00
edn_csr_aliasing 1.980s 79.618us 1 1 100.00
edn_same_csr_outstanding 2.060s 62.070us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 7.720s 1.128ms 1 1 100.00
edn_tl_intg_err 2.700s 79.162us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.660s 26.752us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.800s 83.439us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.720s 1.128ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.720s 1.128ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.720s 1.128ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.720s 1.128ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.800s 83.439us 1 1 100.00
edn_sec_cm 7.720s 1.128ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.800s 83.439us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.700s 79.162us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets