HMAC Simulation Results

Wednesday May 14 2025 18:36:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 9.170s 3.960ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.910s 289.618us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.710s 35.049us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.570s 869.094us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.510s 227.571us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.630s 96.935us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.710s 35.049us 1 1 100.00
hmac_csr_aliasing 3.510s 227.571us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 39.460s 12.469ms 1 1 100.00
V2 back_pressure hmac_back_pressure 23.240s 1.789ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.212m 6.686ms 1 1 100.00
hmac_test_sha384_vectors 5.882m 39.953ms 1 1 100.00
hmac_test_sha512_vectors 5.757m 12.212ms 1 1 100.00
hmac_test_hmac256_vectors 8.640s 3.943ms 1 1 100.00
hmac_test_hmac384_vectors 10.100s 3.269ms 1 1 100.00
hmac_test_hmac512_vectors 10.800s 504.216us 1 1 100.00
V2 burst_wr hmac_burst_wr 17.110s 1.673ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 14.604m 5.915ms 1 1 100.00
V2 error hmac_error 15.150s 3.218ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 56.950s 2.861ms 1 1 100.00
V2 save_and_restore hmac_smoke 9.170s 3.960ms 1 1 100.00
hmac_long_msg 39.460s 12.469ms 1 1 100.00
hmac_back_pressure 23.240s 1.789ms 1 1 100.00
hmac_datapath_stress 14.604m 5.915ms 1 1 100.00
hmac_burst_wr 17.110s 1.673ms 1 1 100.00
hmac_stress_all 10.450s 1.380ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 9.170s 3.960ms 1 1 100.00
hmac_long_msg 39.460s 12.469ms 1 1 100.00
hmac_back_pressure 23.240s 1.789ms 1 1 100.00
hmac_datapath_stress 14.604m 5.915ms 1 1 100.00
hmac_wipe_secret 56.950s 2.861ms 1 1 100.00
hmac_test_sha256_vectors 3.212m 6.686ms 1 1 100.00
hmac_test_sha384_vectors 5.882m 39.953ms 1 1 100.00
hmac_test_sha512_vectors 5.757m 12.212ms 1 1 100.00
hmac_test_hmac256_vectors 8.640s 3.943ms 1 1 100.00
hmac_test_hmac384_vectors 10.100s 3.269ms 1 1 100.00
hmac_test_hmac512_vectors 10.800s 504.216us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 9.170s 3.960ms 1 1 100.00
hmac_long_msg 39.460s 12.469ms 1 1 100.00
hmac_back_pressure 23.240s 1.789ms 1 1 100.00
hmac_datapath_stress 14.604m 5.915ms 1 1 100.00
hmac_burst_wr 17.110s 1.673ms 1 1 100.00
hmac_error 15.150s 3.218ms 1 1 100.00
hmac_wipe_secret 56.950s 2.861ms 1 1 100.00
hmac_test_sha256_vectors 3.212m 6.686ms 1 1 100.00
hmac_test_sha384_vectors 5.882m 39.953ms 1 1 100.00
hmac_test_sha512_vectors 5.757m 12.212ms 1 1 100.00
hmac_test_hmac256_vectors 8.640s 3.943ms 1 1 100.00
hmac_test_hmac384_vectors 10.100s 3.269ms 1 1 100.00
hmac_test_hmac512_vectors 10.800s 504.216us 1 1 100.00
hmac_stress_all 10.450s 1.380ms 1 1 100.00
V2 stress_all hmac_stress_all 10.450s 1.380ms 1 1 100.00
V2 alert_test hmac_alert_test 1.510s 44.653us 1 1 100.00
V2 intr_test hmac_intr_test 1.490s 167.787us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.320s 54.406us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.320s 54.406us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.910s 289.618us 1 1 100.00
hmac_csr_rw 1.710s 35.049us 1 1 100.00
hmac_csr_aliasing 3.510s 227.571us 1 1 100.00
hmac_same_csr_outstanding 1.860s 201.437us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.910s 289.618us 1 1 100.00
hmac_csr_rw 1.710s 35.049us 1 1 100.00
hmac_csr_aliasing 3.510s 227.571us 1 1 100.00
hmac_same_csr_outstanding 1.860s 201.437us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.000s 149.737us 1 1 100.00
hmac_tl_intg_err 3.950s 505.587us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.950s 505.587us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 9.170s 3.960ms 1 1 100.00
V3 stress_reset hmac_stress_reset 6.980s 178.267us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 3.384m 2.293ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 4.140s 200.370us 1 1 100.00
TOTAL 28 28 100.00