I2C Simulation Results

Wednesday May 14 2025 18:36:16 UTC

GitHub Revision: `70ecaeb`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	48.510s	3.268ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	7.520s	3.715ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.570s	58.205us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.480s	46.145us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.790s	230.678us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.400s	124.581us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.000s	146.932us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.480s	46.145us	1	1	100.00
		i2c_csr_aliasing	2.400s	124.581us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.880s	256.616us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	3.356m	31.569ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	1.212m	2.749ms	1	1	100.00
V2	host_override	i2c_host_override	1.790s	28.450us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	33.220s	16.656ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	59.000s	5.863ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.900s	675.808us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.300s	564.139us	1	1	100.00
		i2c_host_fifo_reset_rx	4.540s	199.985us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.595m	9.358ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	18.280s	622.906us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.250s	239.238us	1	1	100.00
V2	target_glitch	i2c_target_glitch	7.160s	17.832ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	2.044m	41.424ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.800s	3.366ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	5.100s	603.714us	1	1	100.00
		i2c_target_intr_smoke	5.470s	24.932ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.160s	1.518ms	1	1	100.00
		i2c_target_fifo_reset_tx	1.840s	309.926us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	16.120s	28.801ms	1	1	100.00
		i2c_target_stress_rd	5.100s	603.714us	1	1	100.00
		i2c_target_intr_stress_wr	4.138m	21.060ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.590s	23.942ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	31.450s	1.252ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.520s	1.493ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	20.030s	10.146ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.560s	343.072us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.650s	279.570us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.212m	2.749ms	1	1	100.00
		i2c_host_perf_precise	1.349m	2.541ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	18.280s	622.906us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.890s	300.911us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.900s	2.277ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.590s	3.597ms	1	1	100.00
		i2c_target_nack_txstretch	2.150s	609.577us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	6.030s	490.528us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.470s	452.229us	1	1	100.00
V2	alert_test	i2c_alert_test	1.400s	46.761us	1	1	100.00
V2	intr_test	i2c_intr_test	1.510s	15.787us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.920s	149.444us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.920s	149.444us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.570s	58.205us	1	1	100.00
		i2c_csr_rw	1.480s	46.145us	1	1	100.00
		i2c_csr_aliasing	2.400s	124.581us	1	1	100.00
		i2c_same_csr_outstanding	1.890s	51.295us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.570s	58.205us	1	1	100.00
		i2c_csr_rw	1.480s	46.145us	1	1	100.00
		i2c_csr_aliasing	2.400s	124.581us	1	1	100.00
		i2c_same_csr_outstanding	1.890s	51.295us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	1.890s	128.169us	1	1	100.00
		i2c_sec_cm	1.710s	421.007us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.890s	128.169us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	11.290s	2.556ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.280s	199.580us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	12.860s	3.292ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.34586518322839298377699108609733713317331624466042791531775131947616508988891
    Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2556365930 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2556365930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.43348249865165812106709838911083453991132335651587667008623657080956409399750
    Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3292399222 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3292399222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.8690542449490818120365804436536655862189358693222342162029195525111696202731
Line 285, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 31568968982 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2674890

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.86771813410059411811451586424404965661682205243453475160420917122998599681787
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 199579898 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 90 [0x5a])
  UVM_INFO @ 199579898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.75351612322953290855153686784172450953678845452044798393155358901022713288578
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10146061842 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10146061842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```