KEYMGR Simulation Results

Wednesday May 14 2025 18:36:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.670s	58.505us	1	1	100.00
V1	random	keymgr_random	4.380s	663.061us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.890s	100.279us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.990s	88.109us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	17.880s	10.705ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	4.510s	189.659us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.930s	16.245us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.990s	88.109us	1	1	100.00
		keymgr_csr_aliasing	4.510s	189.659us	0	1	0.00
V1		TOTAL			5	7	71.43
V2	cfgen_during_op	keymgr_cfg_regwen	9.450s	263.524us	1	1	100.00
V2	sideload	keymgr_sideload	2.840s	127.869us	1	1	100.00
		keymgr_sideload_kmac	3.330s	49.530us	1	1	100.00
		keymgr_sideload_aes	4.280s	176.131us	1	1	100.00
		keymgr_sideload_otbn	11.580s	766.207us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.610s	491.194us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.830s	344.247us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.820s	92.258us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	4.370s	453.567us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.450s	308.452us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.350s	58.500us	1	1	100.00
V2	stress_all	keymgr_stress_all	8.700s	486.893us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.850s	85.725us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.760s	16.456us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.700s	320.747us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.700s	320.747us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.890s	100.279us	1	1	100.00
		keymgr_csr_rw	1.990s	88.109us	1	1	100.00
		keymgr_csr_aliasing	4.510s	189.659us	0	1	0.00
		keymgr_same_csr_outstanding	2.790s	97.790us	0	1	0.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.890s	100.279us	1	1	100.00
		keymgr_csr_rw	1.990s	88.109us	1	1	100.00
		keymgr_csr_aliasing	4.510s	189.659us	0	1	0.00
		keymgr_same_csr_outstanding	2.790s	97.790us	0	1	0.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	15.030s	703.810us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	15.030s	703.810us	1	1	100.00
		keymgr_tl_intg_err	6.600s	407.666us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.710s	199.522us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.710s	199.522us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.710s	199.522us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.710s	199.522us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	4.790s	194.426us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	15.030s	703.810us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	15.030s	703.810us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	6.600s	407.666us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.710s	199.522us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	9.450s	263.524us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.380s	663.061us	1	1	100.00
		keymgr_csr_rw	1.990s	88.109us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.380s	663.061us	1	1	100.00
		keymgr_csr_rw	1.990s	88.109us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.380s	663.061us	1	1	100.00
		keymgr_csr_rw	1.990s	88.109us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.830s	344.247us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.450s	308.452us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.450s	308.452us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.380s	663.061us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.330s	99.493us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	15.030s	703.810us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	15.030s	703.810us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	15.030s	703.810us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	6.160s	971.693us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.830s	344.247us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	15.030s	703.810us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	15.030s	703.810us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	15.030s	703.810us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	6.160s	971.693us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	6.160s	971.693us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	15.030s	703.810us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	6.160s	971.693us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	15.030s	703.810us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	6.160s	971.693us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	5.190s	498.228us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			26	30	86.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 3 failures:

  • Test keymgr_csr_aliasing has 1 failures.

    • 0.keymgr_csr_aliasing.36928677075373881363215767046361547670892776861744467839564011163515562152576
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
        UVM_ERROR @ 189658840 ps: (keymgr_csr_assert_fpv.sv:454) [ASSERT FAILED] attest_sw_binding_4_rd_A
        UVM_INFO @ 189658840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_same_csr_outstanding has 1 failures.

    • 0.keymgr_same_csr_outstanding.22060945241526932604581430236581729009423212866351379659534168051172211089020
      Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
        UVM_ERROR @  97789721 ps: (keymgr_csr_assert_fpv.sv:394) [ASSERT FAILED] sealing_sw_binding_0_rd_A
        UVM_INFO @  97789721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.keymgr_csr_mem_rw_with_rand_reset.60190872517377950273177290884719718946450640426047194797955312524288116111303
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[6] & 'hffffffff)))'
        UVM_ERROR @  16244897 ps: (keymgr_csr_assert_fpv.sv:399) [ASSERT FAILED] sealing_sw_binding_1_rd_A
        UVM_INFO @  16244897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.34527900823050099239968337800318301812648531229593396942594604060377524765013
      Line 185, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 498228009 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 498228009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---