KMAC/MASKED Simulation Results

Wednesday May 14 2025 18:36:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	25.300s	952.549us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.070s	59.786us	1	1	100.00
V1	csr_rw	kmac_csr_rw	2.200s	26.467us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	11.830s	1.170ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.960s	93.332us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.630s	815.183us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.200s	26.467us	1	1	100.00
		kmac_csr_aliasing	4.960s	93.332us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.640s	15.831us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.870s	35.102us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	2.220s	54.011us	0	1	0.00
V2	burst_write	kmac_burst_write	17.713m	50.313ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.711m	124.040ms	1	1	100.00
		kmac_test_vectors_sha3_256	23.833m	66.529ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.117m	26.118ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.790s	2.845ms	1	1	100.00
		kmac_test_vectors_shake_128	3.243m	64.442ms	1	1	100.00
		kmac_test_vectors_shake_256	4.821m	16.144ms	1	1	100.00
		kmac_test_vectors_kmac	3.140s	263.782us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.200s	43.121us	1	1	100.00
V2	sideload	kmac_sideload	2.010m	23.418ms	1	1	100.00
V2	app	kmac_app	2.360m	6.659ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.670s	239.061us	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	30.110s	24.434ms	1	1	100.00
V2	error	kmac_error	6.049m	57.288ms	1	1	100.00
V2	key_error	kmac_key_error	9.180s	2.193ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.420s	59.563us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	2.020s	79.864us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.710s	75.665us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	11.260s	1.263ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.460s	32.685us	1	1	100.00
V2	stress_all	kmac_stress_all	12.104m	156.625ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.660s	28.152us	1	1	100.00
V2	alert_test	kmac_alert_test	1.880s	21.791us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.240s	210.323us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.240s	210.323us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.070s	59.786us	1	1	100.00
		kmac_csr_rw	2.200s	26.467us	1	1	100.00
		kmac_csr_aliasing	4.960s	93.332us	1	1	100.00
		kmac_same_csr_outstanding	2.590s	42.866us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.070s	59.786us	1	1	100.00
		kmac_csr_rw	2.200s	26.467us	1	1	100.00
		kmac_csr_aliasing	4.960s	93.332us	1	1	100.00
		kmac_same_csr_outstanding	2.590s	42.866us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.620s	109.608us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.620s	109.608us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.620s	109.608us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.620s	109.608us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.010s	407.569us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	43.740s	17.739ms	1	1	100.00
		kmac_tl_intg_err	4.810s	760.633us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.810s	760.633us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.460s	32.685us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	25.300s	952.549us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.010m	23.418ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.620s	109.608us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	43.740s	17.739ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	43.740s	17.739ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	43.740s	17.739ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	25.300s	952.549us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.460s	32.685us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	43.740s	17.739ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	26.790s	1.269ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	25.300s	952.549us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.790m	7.393ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_long_msg_and_output has 1 failures.

    • 0.kmac_long_msg_and_output.74953219416608468532877813029613200818845375071138269770580472481524555764386
      Line 72, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest/run.log

        UVM_ERROR @  54011213 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  54011213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.99513126949335069225251323863748245386649920690410668548816344528980682839997
      Line 187, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7392909001 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 7392909001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---