KMAC/UNMASKED Simulation Results

Wednesday May 14 2025 18:36:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	20.260s	8.032ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.320s	108.227us	1	1	100.00
V1	csr_rw	kmac_csr_rw	2.150s	53.970us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.440s	2.999ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.340s	77.137us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.530s	244.210us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.150s	53.970us	1	1	100.00
		kmac_csr_aliasing	4.340s	77.137us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.680s	33.212us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.420s	22.187us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	9.132m	50.849ms	1	1	100.00
V2	burst_write	kmac_burst_write	3.051m	3.094ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	26.619m	64.753ms	1	1	100.00
		kmac_test_vectors_sha3_256	34.360s	7.195ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.950s	855.376us	1	1	100.00
		kmac_test_vectors_sha3_512	9.240m	17.276ms	1	1	100.00
		kmac_test_vectors_shake_128	1.983m	13.865ms	1	1	100.00
		kmac_test_vectors_shake_256	3.270m	21.704ms	1	1	100.00
		kmac_test_vectors_kmac	2.680s	167.243us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.220s	159.122us	1	1	100.00
V2	sideload	kmac_sideload	2.219m	46.584ms	1	1	100.00
V2	app	kmac_app	16.110s	1.272ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.333m	5.721ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	50.890s	5.782ms	1	1	100.00
V2	error	kmac_error	3.853m	4.540ms	1	1	100.00
V2	key_error	kmac_key_error	3.030s	574.320us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.620s	81.864us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	15.200s	812.451us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	16.460s	2.019ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	9.930s	2.733ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	9.400s	3.182ms	1	1	100.00
V2	stress_all	kmac_stress_all	4.905m	20.326ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.900s	14.689us	1	1	100.00
V2	alert_test	kmac_alert_test	1.680s	46.263us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.160s	128.250us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.160s	128.250us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.320s	108.227us	1	1	100.00
		kmac_csr_rw	2.150s	53.970us	1	1	100.00
		kmac_csr_aliasing	4.340s	77.137us	1	1	100.00
		kmac_same_csr_outstanding	2.990s	91.683us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.320s	108.227us	1	1	100.00
		kmac_csr_rw	2.150s	53.970us	1	1	100.00
		kmac_csr_aliasing	4.340s	77.137us	1	1	100.00
		kmac_same_csr_outstanding	2.990s	91.683us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.990s	32.171us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.990s	32.171us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.990s	32.171us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.990s	32.171us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.020s	675.038us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	49.720s	11.205ms	1	1	100.00
		kmac_tl_intg_err	3.800s	566.414us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.800s	566.414us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	9.400s	3.182ms	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	20.260s	8.032ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.219m	46.584ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.990s	32.171us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	49.720s	11.205ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	49.720s	11.205ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	49.720s	11.205ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	20.260s	8.032ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	9.400s	3.182ms	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	49.720s	11.205ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	10.450s	894.594us	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	20.260s	8.032ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.173m	34.288ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.37755784840100052699144490605385017153445991636495190934139444235574052511886
      Line 311, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 34288386011 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 34288386011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---