PATTGEN Simulation Results

Wednesday May 14 2025 18:36:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	4.000s	90.212us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	6.000s	49.853us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	6.000s	40.970us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	129.657us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	26.114us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	25.687us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	6.000s	40.970us	1	1	100.00
		pattgen_csr_aliasing	4.000s	26.114us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	22.000s	4.538ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	10.000s	814.767us	1	1	100.00
V2	error	pattgen_error	4.000s	168.283us	1	1	100.00
V2	stress_all	pattgen_stress_all			0	1	0.00
V2	alert_test	pattgen_alert_test	4.000s	10.079us	1	1	100.00
V2	intr_test	pattgen_intr_test	10.000s	12.643us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	11.000s	51.916us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	11.000s	51.916us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	6.000s	49.853us	1	1	100.00
		pattgen_csr_rw	6.000s	40.970us	1	1	100.00
		pattgen_csr_aliasing	4.000s	26.114us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	48.949us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	6.000s	49.853us	1	1	100.00
		pattgen_csr_rw	6.000s	40.970us	1	1	100.00
		pattgen_csr_aliasing	4.000s	26.114us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	48.949us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	10.000s	61.120us	1	1	100.00
		pattgen_sec_cm	4.000s	37.866us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	10.000s	61.120us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	38.000s	5.501ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	4.000s	31.289us	1	1	100.00
		TOTAL			16	18	88.89

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.54681630520428855317699622544525289675421125875751218237538666628896845917325
      Line 240, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1403948156 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 1403967461 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1403967461 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 4/10
        UVM_INFO @ 1404130725 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
      

• Job timed out after * minutes has 1 failures:

  • Test pattgen_stress_all has 1 failures.

    • 0.pattgen_stress_all.85707474227634779131817620063940598289067440001345887792421174792565310756189
      Log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log

        Job timed out after 180 minutes