ROM_CTRL/64KB Simulation Results

Wednesday May 14 2025 18:36:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.120s 825.504us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.080s 296.839us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.470s 1.070ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.010s 1.071ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.000s 371.111us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.980s 354.987us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.470s 1.070ms 1 1 100.00
rom_ctrl_csr_aliasing 7.000s 371.111us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.000s 1.681ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.730s 210.274us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.560s 407.158us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 28.530s 1.092ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 14.230s 572.558us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.760s 1.684ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.730s 712.456us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.730s 712.456us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.080s 296.839us 1 1 100.00
rom_ctrl_csr_rw 6.470s 1.070ms 1 1 100.00
rom_ctrl_csr_aliasing 7.000s 371.111us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.860s 1.025ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.080s 296.839us 1 1 100.00
rom_ctrl_csr_rw 6.470s 1.070ms 1 1 100.00
rom_ctrl_csr_aliasing 7.000s 371.111us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.860s 1.025ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.822m 3.150ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 37.180s 6.374ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.217m 6.409ms 1 1 100.00
rom_ctrl_tl_intg_err 37.500s 1.125ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.217m 6.409ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.217m 6.409ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.822m 3.150ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.822m 3.150ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.822m 3.150ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.822m 3.150ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.822m 3.150ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.217m 6.409ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.217m 6.409ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.120s 825.504us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.120s 825.504us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.120s 825.504us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 37.500s 1.125ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.822m 3.150ms 1 1 100.00
rom_ctrl_kmac_err_chk 14.230s 572.558us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.822m 3.150ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.822m 3.150ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.822m 3.150ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 37.180s 6.374ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.217m 6.409ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.458m 21.348ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00