RV_DM/USE_JTAG_INTERFACE Simulation Results

Wednesday May 14 2025 18:36:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 3.570s 1.150ms 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 2.390s 596.759us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.290s 528.763us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 5.870s 2.499ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.720s 489.089us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 31.950s 18.179ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 2.390s 1.935ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 5.232m 175.130ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.166m 79.570ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.750s 302.076us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.770s 359.993us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.950s 143.288us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.120s 451.938us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 2.460s 439.251us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.860s 189.724us 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.600s 167.221us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 1.890s 292.129us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.750s 302.076us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.620s 247.927us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.860s 512.208us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.950s 143.288us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.620s 64.288us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.750s 133.206us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.280s 117.185us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 36.260s 2.421ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 57.740s 47.562ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.790s 27.032us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 57.740s 47.562ms 1 1 100.00
rv_dm_csr_rw 2.280s 117.185us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.550s 42.462us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.600s 32.016us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 3.570s 1.150ms 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.810s 686.598us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 2.340s 312.655us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.880s 161.099us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 3.000s 882.719us 1 1 100.00
V2 sba rv_dm_sba_tl_access 5.730s 4.724ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 1.860s 342.729us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 2.710s 2.123ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 36.310s 18.963ms 1 1 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.590s 286.516us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 2.470s 550.616us 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 2.740s 378.381us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 2.290s 184.986us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 3.660s 4.914ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 1.720s 89.808us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 2.170s 279.645us 1 1 100.00
V2 stress_all rv_dm_stress_all 3.470s 3.576ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.780s 33.704us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.610s 35.091us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.610s 35.091us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 57.740s 47.562ms 1 1 100.00
rv_dm_csr_hw_reset 2.750s 133.206us 1 1 100.00
rv_dm_csr_rw 2.280s 117.185us 1 1 100.00
rv_dm_same_csr_outstanding 6.550s 2.375ms 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 57.740s 47.562ms 1 1 100.00
rv_dm_csr_hw_reset 2.750s 133.206us 1 1 100.00
rv_dm_csr_rw 2.280s 117.185us 1 1 100.00
rv_dm_same_csr_outstanding 6.550s 2.375ms 1 1 100.00
V2 TOTAL 16 19 84.21
V2S tl_intg_err rv_dm_sec_cm 4.230s 1.163ms 1 1 100.00
rv_dm_tl_intg_err 11.770s 3.379ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 11.770s 3.379ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 2.470s 550.616us 1 1 100.00
rv_dm_debug_disabled 1.840s 32.472us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 2.470s 550.616us 1 1 100.00
rv_dm_debug_disabled 1.840s 32.472us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 3.570s 1.150ms 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 2.050s 483.672us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.920s 249.693us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.920s 249.693us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 2.050s 483.672us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.770s 30.333us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.740s 19.015us 1 1 100.00
TOTAL 48 53 90.57

Failure Buckets