RV_TIMER Simulation Results

Wednesday May 14 2025 18:36:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.490s	60.914us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.560s	44.000us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.720s	24.044us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.960s	284.521us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.070s	53.372us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.900s	50.815us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.720s	24.044us	1	1	100.00
		rv_timer_csr_aliasing	2.070s	53.372us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.730s	215.239us	1	1	100.00
V2	disabled	rv_timer_disabled	3.140s	1.604ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	1.697m	83.581ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	1.697m	83.581ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.340s	5.783ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.280s	12.439us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.500s	37.208us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.970s	744.868us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.970s	744.868us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.560s	44.000us	1	1	100.00
		rv_timer_csr_rw	1.720s	24.044us	1	1	100.00
		rv_timer_csr_aliasing	2.070s	53.372us	1	1	100.00
		rv_timer_same_csr_outstanding	1.550s	31.392us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.560s	44.000us	1	1	100.00
		rv_timer_csr_rw	1.720s	24.044us	1	1	100.00
		rv_timer_csr_aliasing	2.070s	53.372us	1	1	100.00
		rv_timer_same_csr_outstanding	1.550s	31.392us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.050s	384.516us	1	1	100.00
		rv_timer_tl_intg_err	1.990s	1.164ms	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.990s	1.164ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	35.210s	26.231ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.400s	21.731us	1	1	100.00
		rv_timer_max	1.570s	218.198us	1	1	100.00
		TOTAL			19	19	100.00