SPI_DEVICE/1R1W Simulation Results

Wednesday May 14 2025 18:36:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	24.490s	13.188ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.990s	83.093us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	3.010s	39.691us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	19.020s	1.220ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.370s	323.040us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.600s	917.116us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.010s	39.691us	1	1	100.00
		spi_device_csr_aliasing	6.370s	323.040us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.590s	56.625us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.300s	106.096us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.830s	58.155us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.560s	5.377us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.580s	5.558us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.070s	134.748us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.070s	134.748us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	6.580s	1.674ms	1	1	100.00
		spi_device_tpm_sts_read	1.760s	27.573us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	15.110s	4.887ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.630s	785.058us	1	1	100.00
		spi_device_flash_all	33.580s	9.548ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.650s	308.861us	1	1	100.00
		spi_device_flash_all	33.580s	9.548ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.650s	308.861us	1	1	100.00
		spi_device_flash_all	33.580s	9.548ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	33.580s	9.548ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	8.980s	1.140ms	1	1	100.00
		spi_device_flash_all	33.580s	9.548ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	8.980s	1.140ms	1	1	100.00
		spi_device_flash_all	33.580s	9.548ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	8.980s	1.140ms	1	1	100.00
		spi_device_flash_all	33.580s	9.548ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	8.980s	1.140ms	1	1	100.00
		spi_device_flash_all	33.580s	9.548ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	8.980s	1.140ms	1	1	100.00
		spi_device_flash_all	33.580s	9.548ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	7.490s	1.244ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	6.590s	308.061us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	6.590s	308.061us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	6.590s	308.061us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	46.960s	4.898ms	1	1	100.00
		spi_device_read_buffer_direct	5.750s	4.106ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	6.590s	308.061us	1	1	100.00
		spi_device_flash_all	33.580s	9.548ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	33.580s	9.548ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	33.580s	9.548ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.720s	398.818us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.720s	398.818us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	24.490s	13.188ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.171m	25.506ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.220s	54.608us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.630s	21.423us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.730s	102.668us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.490s	429.995us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.490s	429.995us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.990s	83.093us	1	1	100.00
		spi_device_csr_rw	3.010s	39.691us	1	1	100.00
		spi_device_csr_aliasing	6.370s	323.040us	1	1	100.00
		spi_device_same_csr_outstanding	2.620s	73.429us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.990s	83.093us	1	1	100.00
		spi_device_csr_rw	3.010s	39.691us	1	1	100.00
		spi_device_csr_aliasing	6.370s	323.040us	1	1	100.00
		spi_device_same_csr_outstanding	2.620s	73.429us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.050s	94.455us	1	1	100.00
		spi_device_tl_intg_err	13.280s	3.869ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	13.280s	3.869ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.248m	34.679ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.18981276847511207104872105481436802390967396389998519266459102979815053893755
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4656611 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[33])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4656611 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4656611 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[929])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.13694469902401147085741108131465040205969270027212420945732328083699663435083
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   2930491 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xafa85f [101011111010100001011111] vs 0x0 [0])
        UVM_ERROR @   2973491 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbb4dd3 [101110110100110111010011] vs 0x0 [0])
        UVM_ERROR @   3031491 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x628bfd [11000101000101111111101] vs 0x0 [0])
        UVM_ERROR @   3071491 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5077c [1010000011101111100] vs 0x0 [0])
        UVM_ERROR @   3099491 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x57c964 [10101111100100101100100] vs 0x0 [0])