SPI_DEVICE/2P Simulation Results

Wednesday May 14 2025 18:36:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 42.510s 6.722ms 1 1 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.760s 84.447us 1 1 100.00
V1 csr_rw spi_device_csr_rw 1.840s 30.326us 1 1 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 9.880s 2.421ms 1 1 100.00
V1 csr_aliasing spi_device_csr_aliasing 6.180s 332.878us 1 1 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 3.980s 2.192ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 1.840s 30.326us 1 1 100.00
spi_device_csr_aliasing 6.180s 332.878us 1 1 100.00
V1 mem_walk spi_device_mem_walk 1.710s 22.561us 1 1 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.890s 195.440us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 csb_read spi_device_csb_read 1.710s 50.049us 1 1 100.00
V2 mem_parity spi_device_mem_parity 1.700s 128.472us 1 1 100.00
V2 mem_cfg spi_device_ram_cfg 1.720s 26.106us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 1.740s 38.066us 1 1 100.00
V2 tpm_write spi_device_tpm_rw 1.740s 38.066us 1 1 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 11.320s 59.393ms 1 1 100.00
spi_device_tpm_sts_read 1.890s 33.754us 1 1 100.00
V2 tpm_fully_random_case spi_device_tpm_all 20.570s 22.950ms 1 1 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 6.490s 535.509us 1 1 100.00
spi_device_flash_all 1.178m 16.919ms 1 1 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 12.870s 102.569ms 1 1 100.00
spi_device_flash_all 1.178m 16.919ms 1 1 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 12.870s 102.569ms 1 1 100.00
spi_device_flash_all 1.178m 16.919ms 1 1 100.00
V2 cmd_info_slots spi_device_flash_all 1.178m 16.919ms 1 1 100.00
V2 cmd_read_status spi_device_intercept 7.220s 661.782us 1 1 100.00
spi_device_flash_all 1.178m 16.919ms 1 1 100.00
V2 cmd_read_jedec spi_device_intercept 7.220s 661.782us 1 1 100.00
spi_device_flash_all 1.178m 16.919ms 1 1 100.00
V2 cmd_read_sfdp spi_device_intercept 7.220s 661.782us 1 1 100.00
spi_device_flash_all 1.178m 16.919ms 1 1 100.00
V2 cmd_fast_read spi_device_intercept 7.220s 661.782us 1 1 100.00
spi_device_flash_all 1.178m 16.919ms 1 1 100.00
V2 cmd_read_pipeline spi_device_intercept 7.220s 661.782us 1 1 100.00
spi_device_flash_all 1.178m 16.919ms 1 1 100.00
V2 flash_cmd_upload spi_device_upload 8.550s 15.346ms 1 1 100.00
V2 mailbox_command spi_device_mailbox 32.840s 38.273ms 1 1 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 32.840s 38.273ms 1 1 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 32.840s 38.273ms 1 1 100.00
V2 cmd_read_buffer spi_device_flash_mode 25.970s 2.129ms 1 1 100.00
spi_device_read_buffer_direct 3.890s 104.219us 1 1 100.00
V2 cmd_dummy_cycle spi_device_mailbox 32.840s 38.273ms 1 1 100.00
spi_device_flash_all 1.178m 16.919ms 1 1 100.00
V2 quad_spi spi_device_flash_all 1.178m 16.919ms 1 1 100.00
V2 dual_spi spi_device_flash_all 1.178m 16.919ms 1 1 100.00
V2 4b_3b_feature spi_device_cfg_cmd 5.720s 3.481ms 1 1 100.00
V2 write_enable_disable spi_device_cfg_cmd 5.720s 3.481ms 1 1 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 42.510s 6.722ms 1 1 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 3.540s 4.249ms 1 1 100.00
V2 stress_all spi_device_stress_all 6.313m 212.220ms 1 1 100.00
V2 alert_test spi_device_alert_test 1.600s 64.725us 1 1 100.00
V2 intr_test spi_device_intr_test 1.880s 15.536us 1 1 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 4.500s 349.998us 1 1 100.00
V2 tl_d_illegal_access spi_device_tl_errors 4.500s 349.998us 1 1 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.760s 84.447us 1 1 100.00
spi_device_csr_rw 1.840s 30.326us 1 1 100.00
spi_device_csr_aliasing 6.180s 332.878us 1 1 100.00
spi_device_same_csr_outstanding 2.200s 92.030us 1 1 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.760s 84.447us 1 1 100.00
spi_device_csr_rw 1.840s 30.326us 1 1 100.00
spi_device_csr_aliasing 6.180s 332.878us 1 1 100.00
spi_device_same_csr_outstanding 2.200s 92.030us 1 1 100.00
V2 TOTAL 22 22 100.00
V2S tl_intg_err spi_device_sec_cm 2.300s 626.116us 1 1 100.00
spi_device_tl_intg_err 17.150s 826.641us 1 1 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 17.150s 826.641us 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests spi_device_flash_mode_ignore_cmds 6.930s 377.327us 1 1 100.00
TOTAL 33 33 100.00