SPI_HOST Simulation Results

Wednesday May 14 2025 18:36:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.067m	20.422ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	19.276us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	16.770us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	125.682us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	22.388us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	21.010us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	16.770us	1	1	100.00
		spi_host_csr_aliasing	4.000s	22.388us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	14.628us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	35.791us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	56.055us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	63.756us	1	1	100.00
		spi_host_error_cmd	4.000s	55.401us	1	1	100.00
		spi_host_event	31.000s	3.798ms	1	1	100.00
V2	clock_rate	spi_host_speed	5.000s	224.908us	1	1	100.00
V2	speed	spi_host_speed	5.000s	224.908us	1	1	100.00
V2	chip_select_timing	spi_host_speed	5.000s	224.908us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	5.000s	57.528us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	84.061us	1	1	100.00
V2	cpol_cpha	spi_host_speed	5.000s	224.908us	1	1	100.00
V2	full_cycle	spi_host_speed	5.000s	224.908us	1	1	100.00
V2	duplex	spi_host_smoke	1.067m	20.422ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	1.067m	20.422ms	1	1	100.00
V2	stress_all	spi_host_stress_all	5.000s	288.133us	1	1	100.00
V2	spien	spi_host_spien	6.000s	120.495us	1	1	100.00
V2	stall	spi_host_status_stall	17.000s	1.551ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	414.014us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	63.756us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	56.903us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	40.713us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	104.212us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	104.212us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	19.276us	1	1	100.00
		spi_host_csr_rw	4.000s	16.770us	1	1	100.00
		spi_host_csr_aliasing	4.000s	22.388us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	106.178us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	19.276us	1	1	100.00
		spi_host_csr_rw	4.000s	16.770us	1	1	100.00
		spi_host_csr_aliasing	4.000s	22.388us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	106.178us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	217.119us	1	1	100.00
		spi_host_sec_cm	4.000s	39.752us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	217.119us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	17.000s	2.199ms	1	1	100.00
		TOTAL			26	26	100.00