SRAM_CTRL/MAIN Simulation Results

Wednesday May 14 2025 18:36:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	9.590s	492.071us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.870s	118.365us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.730s	13.893us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.790s	233.543us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.020s	12.547us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.810s	355.739us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.730s	13.893us	1	1	100.00
		sram_ctrl_csr_aliasing	2.020s	12.547us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.108m	21.097ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.160m	11.811ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.891m	6.330ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.191m	3.651ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	17.553m	21.317ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1.493m	4.192ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	42.950s	12.152ms	1	1	100.00
V2	executable	sram_ctrl_executable	4.333m	9.177ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	14.500s	985.439us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.647m	72.581ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	8.750s	6.919ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	14.980s	1.493ms	1	1	100.00
		sram_ctrl_throughput_w_readback	4.710s	2.664ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	17.491m	308.700ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.010s	709.720us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	36.034m	86.539ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.590s	53.482us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.640s	180.606us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.640s	180.606us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.870s	118.365us	1	1	100.00
		sram_ctrl_csr_rw	1.730s	13.893us	1	1	100.00
		sram_ctrl_csr_aliasing	2.020s	12.547us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.660s	14.848us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.870s	118.365us	1	1	100.00
		sram_ctrl_csr_rw	1.730s	13.893us	1	1	100.00
		sram_ctrl_csr_aliasing	2.020s	12.547us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.660s	14.848us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	35.310s	73.907ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.570s	3.681us	0	1	0.00
		sram_ctrl_tl_intg_err	2.780s	134.982us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.570s	3.681us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.780s	134.982us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	17.491m	308.700ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	17.491m	308.700ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.730s	13.893us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.333m	9.177ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.333m	9.177ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.333m	9.177ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	42.950s	12.152ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.260s	689.100us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	35.310s	73.907ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.590s	689.138us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	9.590s	492.071us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	9.590s	492.071us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.333m	9.177ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.570s	3.681us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	42.950s	12.152ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.570s	3.681us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.570s	3.681us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	9.590s	492.071us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.570s	3.681us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	7.290s	211.335us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.77592525356325346647296601218419391728054463478514494843123149584334616527354
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 689100386 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 689100386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.29609779383417373951671441875429071849071660493772260659536710866665052170444
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   3680785 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   3680785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---