SRAM_CTRL/RET Simulation Results

Wednesday May 14 2025 18:36:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	35.270s	520.859us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.860s	141.816us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.580s	28.884us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.040s	447.274us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.590s	18.782us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.930s	201.839us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.580s	28.884us	1	1	100.00
		sram_ctrl_csr_aliasing	1.590s	18.782us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.160s	592.151us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.640s	69.211us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	multiple_keys	sram_ctrl_multiple_keys	14.592m	103.808ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.060m	5.133ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	25.060s	3.205ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.808m	7.174ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.880s	489.802us	1	1	100.00
V2	executable	sram_ctrl_executable	7.924m	29.481ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	43.640s	2.921ms	1	1	100.00
		sram_ctrl_partial_access_b2b	2.355m	2.684ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	39.000s	115.010us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	24.610s	248.635us	1	1	100.00
		sram_ctrl_throughput_w_readback	16.040s	279.061us	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.514m	9.587ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.740s	42.534us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	20.951m	9.231ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.670s	13.952us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.880s	94.324us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.880s	94.324us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.860s	141.816us	1	1	100.00
		sram_ctrl_csr_rw	1.580s	28.884us	1	1	100.00
		sram_ctrl_csr_aliasing	1.590s	18.782us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.660s	46.640us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.860s	141.816us	1	1	100.00
		sram_ctrl_csr_rw	1.580s	28.884us	1	1	100.00
		sram_ctrl_csr_aliasing	1.590s	18.782us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.660s	46.640us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.390s	1.058ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.610s	5.007us	0	1	0.00
		sram_ctrl_tl_intg_err	2.280s	79.420us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.610s	5.007us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.280s	79.420us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.514m	9.587ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.514m	9.587ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.580s	28.884us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.924m	29.481ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.924m	29.481ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.924m	29.481ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.880s	489.802us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.910s	44.317us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.390s	1.058ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.380s	116.145us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	35.270s	520.859us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	35.270s	520.859us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.924m	29.481ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.610s	5.007us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.880s	489.802us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.610s	5.007us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.610s	5.007us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	35.270s	520.859us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.610s	5.007us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	8.550s	924.986us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'pend_req[d2h.d_source].pend' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.26710887666438579313514903538956841465472823097777522210001518927077729394483
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending 'pend_req[d2h.d_source].pend'
        UVM_ERROR @   5006691 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
        UVM_INFO @   5006691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.sram_ctrl_csr_mem_rw_with_rand_reset.41818862823894595847333168656067869362148479396181853410657192186090594639512
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 201839426 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (12 [0xc] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @ 201839426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---