SYSRST_CTRL Simulation Results

Wednesday May 14 2025 18:36:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 3.630s 2.116ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 2.140s 2.524ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 3.960s 2.414ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 3.830s 2.342ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 2.900s 6.128ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 4.390s 2.051ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 17.350s 40.540ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 7.680s 2.682ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 2.640s 2.164ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 4.390s 2.051ms 1 1 100.00
sysrst_ctrl_csr_aliasing 7.680s 2.682ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 58.390s 125.834ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 31.750s 69.327ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 2.970s 3.010ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 2.620s 2.407ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 4.090s 2.516ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 2.100s 2.130ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 3.530s 4.160ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 2.630s 2.632ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 3.910s 9.771ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 6.330s 29.604ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 13.390s 20.097ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 3.400s 2.024ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 6.500s 2.012ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 4.400s 2.056ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 4.400s 2.056ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 2.900s 6.128ms 1 1 100.00
sysrst_ctrl_csr_rw 4.390s 2.051ms 1 1 100.00
sysrst_ctrl_csr_aliasing 7.680s 2.682ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 13.920s 7.991ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 2.900s 6.128ms 1 1 100.00
sysrst_ctrl_csr_rw 4.390s 2.051ms 1 1 100.00
sysrst_ctrl_csr_aliasing 7.680s 2.682ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 13.920s 7.991ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 11.290s 42.368ms 1 1 100.00
sysrst_ctrl_tl_intg_err 1.339m 42.469ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.339m 42.469ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 9.960s 20.706ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00