UART Simulation Results

Wednesday May 14 2025 18:36:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	4.490s	628.665us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.620s	39.359us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.600s	14.960us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.250s	99.006us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.590s	61.919us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.710s	117.503us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.600s	14.960us	1	1	100.00
		uart_csr_aliasing	1.590s	61.919us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	44.740s	64.056ms	1	1	100.00
V2	parity	uart_smoke	4.490s	628.665us	1	1	100.00
		uart_tx_rx	44.740s	64.056ms	1	1	100.00
V2	parity_error	uart_intr	24.110s	98.507ms	1	1	100.00
		uart_rx_parity_err	41.420s	66.574ms	1	1	100.00
V2	watermark	uart_tx_rx	44.740s	64.056ms	1	1	100.00
		uart_intr	24.110s	98.507ms	1	1	100.00
V2	fifo_full	uart_fifo_full	8.080s	22.131ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	2.235m	221.416ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	17.710s	48.536ms	1	1	100.00
V2	rx_frame_err	uart_intr	24.110s	98.507ms	1	1	100.00
V2	rx_break_err	uart_intr	24.110s	98.507ms	1	1	100.00
V2	rx_timeout	uart_intr	24.110s	98.507ms	1	1	100.00
V2	perf	uart_perf	1.954m	14.883ms	1	1	100.00
V2	sys_loopback	uart_loopback	6.230s	10.059ms	1	1	100.00
V2	line_loopback	uart_loopback	6.230s	10.059ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	11.800s	30.195ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.670s	727.366us	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.810s	1.972ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	17.130s	5.130ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	1.781m	20.158ms	1	1	100.00
V2	stress_all	uart_stress_all	1.508m	245.208ms	1	1	100.00
V2	alert_test	uart_alert_test	1.660s	14.300us	1	1	100.00
V2	intr_test	uart_intr_test	1.510s	29.668us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.040s	111.151us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.040s	111.151us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.620s	39.359us	1	1	100.00
		uart_csr_rw	1.600s	14.960us	1	1	100.00
		uart_csr_aliasing	1.590s	61.919us	1	1	100.00
		uart_same_csr_outstanding	1.640s	81.512us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.620s	39.359us	1	1	100.00
		uart_csr_rw	1.600s	14.960us	1	1	100.00
		uart_csr_aliasing	1.590s	61.919us	1	1	100.00
		uart_same_csr_outstanding	1.640s	81.512us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	2.070s	40.669us	1	1	100.00
		uart_tl_intg_err	2.180s	1.691ms	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.180s	1.691ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.385m	15.814ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00