CHIP Simulation Results

Wednesday May 14 2025 18:36:16 UTC

GitHub Revision: `70ecaeb`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.056m	3.192ms	1	1	100.00
		chip_sw_example_rom	1.159m	2.371ms	1	1	100.00
		chip_sw_example_manufacturer	2.392m	2.661ms	1	1	100.00
		chip_sw_example_concurrency	2.787m	2.957ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.158m	4.072ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.501m	3.866ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	9.635m	9.122ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	58.843m	27.710ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	49.090s	2.376ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	58.843m	27.710ms	1	1	100.00
		chip_csr_rw	3.501m	3.866ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.260s	219.144us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.103m	3.780ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.103m	3.780ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.103m	3.780ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.541m	4.001ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.541m	4.001ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.987m	4.639ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.149m	4.025ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.259m	4.476ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	14.847m	8.044ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	14.994m	8.306ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	10.279m	8.194ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.277m	5.210ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.277m	5.210ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.432m	2.359ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.821m	2.172ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.715m	3.404ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.994m	3.716ms	1	1	100.00
		chip_tap_straps_testunlock0	3.550m	4.607ms	1	1	100.00
		chip_tap_straps_rma	6.828m	6.357ms	1	1	100.00
		chip_tap_straps_prod	1.285m	2.361ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.274m	2.487ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	14.162m	8.709ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.270m	5.339ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.270m	5.339ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.886m	8.054ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	45.088m	25.562ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.250m	4.193ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.662m	5.095ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.273m	17.890ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.879m	3.154ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	11.012m	7.828ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.933m	3.103ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.385m	7.960ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.557m	2.403ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.186m	4.500ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.191m	2.638ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.144m	3.569ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	9.076m	6.822ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.292m	5.072ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	3.737m	2.773ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.292m	5.072ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.994m	3.332ms	1	1	100.00
		chip_sw_aes_smoketest	2.035m	2.518ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.453m	3.323ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.559m	2.498ms	1	1	100.00
		chip_sw_csrng_smoketest	2.083m	2.264ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.522m	3.916ms	1	1	100.00
		chip_sw_gpio_smoketest	3.250m	3.460ms	1	1	100.00
		chip_sw_hmac_smoketest	3.377m	3.458ms	1	1	100.00
		chip_sw_kmac_smoketest	3.313m	3.398ms	1	1	100.00
		chip_sw_otbn_smoketest	16.812m	10.023ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.082m	4.308ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	5.359m	6.002ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.858m	2.524ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.636m	2.550ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.384m	3.126ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.890m	2.587ms	1	1	100.00
		chip_sw_uart_smoketest	1.991m	3.070ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.809m	2.924ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.729m	3.980ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.979h	60.876ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	40.038m	14.808ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.330m	5.804ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.365m	3.096ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.231m	3.383ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.882h	53.788ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.979h	57.221ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	56.490s	2.162ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	56.490s	2.162ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	58.843m	27.710ms	1	1	100.00
		chip_same_csr_outstanding	22.466m	17.548ms	1	1	100.00
		chip_csr_hw_reset	2.158m	4.072ms	1	1	100.00
		chip_csr_rw	3.501m	3.866ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	58.843m	27.710ms	1	1	100.00
		chip_same_csr_outstanding	22.466m	17.548ms	1	1	100.00
		chip_csr_hw_reset	2.158m	4.072ms	1	1	100.00
		chip_csr_rw	3.501m	3.866ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	48.870s	1.992ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.380s	34.396us	1	1	100.00
		xbar_smoke_large_delays	51.840s	8.541ms	1	1	100.00
		xbar_smoke_slow_rsp	34.690s	3.881ms	1	1	100.00
		xbar_random_zero_delays	14.790s	198.279us	1	1	100.00
		xbar_random_large_delays	2.908m	28.365ms	1	1	100.00
		xbar_random_slow_rsp	38.400s	4.212ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	19.330s	282.135us	1	1	100.00
		xbar_error_and_unmapped_addr	6.050s	50.255us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	36.170s	2.053ms	1	1	100.00
		xbar_error_and_unmapped_addr	6.050s	50.255us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	32.950s	1.220ms	1	1	100.00
		xbar_access_same_device_slow_rsp	27.190s	2.636ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	22.850s	516.372us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	2.203m	6.331ms	1	1	100.00
		xbar_stress_all_with_error	4.208m	13.576ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	4.456m	6.308ms	1	1	100.00
		xbar_stress_all_with_reset_error	2.785m	1.536ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	40.038m	14.808ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	22.286m	18.383ms	0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	39.176m	15.013ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	32.916m	10.964ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	42.361m	15.466ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	40.238m	15.536ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	39.105m	15.608ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	40.073m	14.479ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	29.470s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	28.290s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	28.800s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	28.790s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	30.090s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	30.430s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	27.880s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	28.200s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	30.270s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	30.290s	10.160us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	27.700s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	28.280s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	32.140s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	28.740s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	27.420s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	27.670s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	27.270s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	30.160s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	26.470s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	26.230s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	28.470s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	25.880s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	42.890s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	35.860s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	30.590s	10.380us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	28.985m	10.615ms	1	1	100.00
		rom_e2e_asm_init_dev	39.148m	15.879ms	1	1	100.00
		rom_e2e_asm_init_prod	39.667m	15.876ms	1	1	100.00
		rom_e2e_asm_init_prod_end	40.372m	15.915ms	1	1	100.00
		rom_e2e_asm_init_rma	34.986m	15.468ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	36.967m	14.513ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	37.484m	15.113ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	37.215m	15.032ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	37.703m	15.351ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	44.569m	34.731ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	44.569m	34.731ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.027m	3.464ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.879m	3.154ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.199m	3.023ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.045m	2.546ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	15.497m	9.076ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	3.315m	3.619ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.442m	5.097ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.946m	6.209ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.040m	5.455ms	1	1	100.00
		chip_plic_all_irqs_10	4.295m	3.654ms	1	1	100.00
		chip_plic_all_irqs_20	5.724m	4.268ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.592m	3.853ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	14.136m	10.002ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.304m	3.895ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.768m	3.248ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.011m	11.810ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	15.038m	7.424ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.169m	7.323ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	14.053m	7.968ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.914h	255.348ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.413m	4.238ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.082m	4.308ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.413m	4.238ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.873m	10.129ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.873m	10.129ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.941m	6.354ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.893m	4.266ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.018m	5.878ms	1	1	100.00
		chip_sw_aes_idle	2.045m	2.546ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.440m	2.668ms	1	1	100.00
		chip_sw_kmac_idle	1.736m	1.928ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	5.559m	5.759ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.317m	4.927ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.712m	5.110ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.843m	4.973ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	11.067m	9.735ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.453m	3.915ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.170m	5.016ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.594m	4.106ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.183m	4.830ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.290m	3.966ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.022m	4.250ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.886m	8.054ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	5.407m	5.129ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.594m	4.106ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.183m	4.830ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.250m	4.193ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.662m	5.095ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.273m	17.890ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.879m	3.154ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	11.012m	7.828ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.933m	3.103ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.385m	7.960ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.557m	2.403ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.186m	4.500ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.191m	2.638ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.705m	2.324ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.955m	5.287ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.409m	6.986ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	47.367m	24.390ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.150m	2.252ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.320m	2.630ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	11.295m	7.588ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.643m	2.729ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.958m	5.615ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	18.940m	20.282ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	2.862h	130.308ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.886m	8.054ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	6.200m	5.445ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.761m	3.395ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.946m	6.209ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	15.038m	7.424ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.546m	6.387ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.861m	3.452ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.691m	5.765ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.171m	2.086ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	54.116m	20.701ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.631m	3.132ms	1	1	100.00
		chip_sw_edn_entropy_reqs	12.815m	6.753ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.631m	3.132ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.546m	6.387ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.888m	2.840ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	16.087m	19.230ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	10.625m	5.706ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.662m	5.095ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.528m	3.617ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.250m	4.193ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	51.202m	42.930ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	16.087m	19.230ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.037m	3.311ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	13.064m	7.863ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.901m	5.786ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	51.202m	42.930ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.901m	5.786ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.901m	5.786ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.901m	5.786ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.901m	5.786ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.946m	6.209ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	4.693m	11.508ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.482m	4.886ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.561m	5.385ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.561m	5.385ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.268m	2.885ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.933m	3.103ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.440m	2.668ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.397m	3.132ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	14.780m	7.164ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	7.663m	5.016ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.547m	4.548ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.567m	4.988ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.689m	4.373ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	13.064m	7.863ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.385m	7.960ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	12.794m	7.212ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	15.497m	9.076ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	39.389m	13.182ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.101m	3.136ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.016m	3.455ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.557m	2.403ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	13.064m	7.863ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	9.446m	13.307ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.947m	2.722ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	25.244m	10.780ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.736m	1.928ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.442m	5.097ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.994m	3.716ms	1	1	100.00
		chip_tap_straps_rma	6.828m	6.357ms	1	1	100.00
		chip_tap_straps_prod	1.285m	2.361ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.977m	3.217ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	9.446m	13.307ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	9.446m	13.307ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	9.446m	13.307ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	18.463m	10.889ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.901m	5.786ms	1	1	100.00
		chip_sw_flash_rma_unlocked	51.202m	42.930ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.236m	3.440ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.824m	6.252ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.213m	7.485ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.509m	5.972ms	1	1	100.00
		chip_sw_lc_ctrl_transition	9.446m	13.307ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.064m	7.863ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.559m	10.300ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	7.759m	9.347ms	1	1	100.00
		chip_prim_tl_access	4.693m	11.508ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	5.407m	5.129ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.453m	3.915ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.170m	5.016ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.594m	4.106ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.183m	4.830ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.290m	3.966ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.022m	4.250ms	1	1	100.00
		chip_tap_straps_dev	1.994m	3.716ms	1	1	100.00
		chip_tap_straps_rma	6.828m	6.357ms	1	1	100.00
		chip_tap_straps_prod	1.285m	2.361ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.208m	9.920ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.780m	3.433ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.595m	3.468ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.715m	3.270ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.688m	3.117ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	18.455m	28.515ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.208m	9.920ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.103h	48.343ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	58.203m	51.046ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.006m	10.984ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	58.663m	48.501ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	18.455m	28.515ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.280m	2.024ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.331m	2.503ms	1	1	100.00
		rom_volatile_raw_unlock	1.025m	1.683ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	52.090m	16.423ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.273m	17.890ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.018m	5.878ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.018m	5.878ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.018m	5.878ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.848m	3.222ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	9.446m	13.307ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	16.087m	19.230ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.848m	3.222ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.064m	7.863ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.216m	5.545ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.250m	3.076ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	16.087m	19.230ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.848m	3.222ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.064m	7.863ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.216m	5.545ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.250m	3.076ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	9.446m	13.307ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.378m	4.612ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.977m	3.217ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.236m	3.440ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.824m	6.252ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.213m	7.485ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.509m	5.972ms	1	1	100.00
		chip_sw_lc_ctrl_transition	9.446m	13.307ms	1	1	100.00
		chip_prim_tl_access	4.693m	11.508ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.693m	11.508ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	15.953m	9.084ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.267m	7.716ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	22.965m	30.123ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.022m	7.358ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.308m	7.103ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.918m	5.438ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	16.274m	22.431ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	8.670m	11.246ms	0	1	0.00
		chip_sw_aon_timer_wdog_bite_reset	7.873m	10.129ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	11.852m	12.682ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.742m	4.430ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.267m	7.716ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.070m	4.242ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	40.098m	41.651ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.686m	6.489ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.183m	4.608ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	25.183m	26.051ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.083m	6.490ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	13.980m	10.151ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	22.531m	20.723ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	3.158m	3.461ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.946m	6.209ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.559m	10.300ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.559m	10.300ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	13.980m	10.151ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	25.183m	26.051ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.742m	4.430ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.082m	4.308ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.123m	4.497ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.157m	4.882ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.180m	4.203ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	14.136m	10.002ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.508m	2.682ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.946m	6.209ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	13.169m	7.323ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.415m	4.093ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.382m	4.326ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.363m	2.588ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.250m	3.076ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.157m	4.882ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.157m	4.882ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	25.005m	22.639ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.120m	13.457ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.123m	4.497ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.909m	4.308ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.493m	5.928ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	6.828m	6.357ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.208m	9.920ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.040m	5.455ms	1	1	100.00
		chip_plic_all_irqs_10	4.295m	3.654ms	1	1	100.00
		chip_plic_all_irqs_20	5.724m	4.268ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.500m	2.987ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.805m	2.598ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	40.038m	14.808ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.769m	7.213ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.077m	3.114ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	4.091m	3.977ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.470m	2.848ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.216m	5.545ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.186m	4.500ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	6.571m	8.750ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.547m	6.703ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	7.759m	9.347ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.946m	6.209ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.270m	5.339ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.083m	6.490ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	13.791m	22.110ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.531m	3.100ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.386m	3.195ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.246m	5.129ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	13.791m	22.110ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	13.791m	22.110ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	11.157m	10.983ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	11.157m	10.983ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.227m	5.224ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	44.569m	34.731ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.409m	3.107ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.728m	2.590ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.410m	3.570ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.829m	3.903ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.116m	8.182ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.383h	31.405ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	26.697m	12.401ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.005m	2.388ms	1	1	100.00
V2		TOTAL			237	275	86.18
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.325m	3.202ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	34.230s	1.549ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.517h	72.108ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	14.414m	5.444ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	18.105m	11.099ms	1	1	100.00
		rom_e2e_jtag_debug_dev	15.656m	11.588ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.179m	11.671ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.874m	4.033ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.663m	4.847ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.726m	4.554ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	13.892s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	9.020m	5.041ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.691m	2.870ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	10.649m	4.563ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	12.832m	6.763ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.353m	2.685ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.532m	5.738ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.993m	2.483ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.604m	4.889ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.359m	4.874ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	5.627m	4.731ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	13.980m	10.151ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	18.105m	11.099ms	1	1	100.00
		rom_e2e_jtag_debug_dev	15.656m	11.588ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.179m	11.671ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	6.075m	6.043ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.946m	6.209ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.475h	38.267ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.475h	38.267ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.845m	3.937ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.541m	4.001ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	51.198m	19.300ms	1	1	100.00
V3		TOTAL			22	23	95.65
	Unmapped tests	chip_sival_flash_info_access	2.242m	2.948ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	4.623m	4.654ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	3.055m	3.055ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.827m	2.886ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	4.117m	3.762ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	14.731s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.632m	2.411ms	1	1	100.00
		TOTAL			283	325	87.08

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.48730288805961331449364756246799101530745082909331418438936927353267419458663
    Line 589, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.23808592489319570710610472097532509989041054543638201667002218141691894691103
    Line 627, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.65882729074063288048644006006675242645760272506979273311062087914928447629120
    Line 607, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.113762212994070852513127957506972979719617592369050205021019265227610081216510
    Line 651, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.37472861513532808188832672731443861489617147978849286687163859719039001849342
    Line 647, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.87572371352475195735825721286787953589734418079673345656585541334901255202692
    Line 584, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.5775590142049402329571748814801138844168196388596938607417891539213210962377
    Line 576, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.47127585492649546781461162448055077439651268363521966421514134944977657684175
    Line 599, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.54280664377323955306807639869015462097337367090837426010608529724483000375284
    Line 623, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.77039936896006100736143754249923592765198825436058338192625246644933079542183
    Line 625, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.80925615666058036272560533957762281704776047392613696509509722734906649383056
    Line 686, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.87569232037558292703309288779725052410153991431090250709015937472809679237632
    Line 654, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.17990051281952543857230815057859537197443900707504542840537040445909453261010
    Line 619, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(pend_req[h2d.a_source].pend == *)' has 2 failures:
- Test chip_sw_pwrmgr_deep_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.60137596740867844692991308328617931092421232692444099966446346508243421327576
    Line 457, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log
```
      Offending '(pend_req[h2d.a_source].pend == 0)'
  UVM_ERROR @ 11246.360556 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
  UVM_INFO @ 11246.360556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_shutdown_output has 1 failures.
  - 0.rom_e2e_shutdown_output.80439194252694371685892267702773724486029822676436096929558983826982916897092
    Line 550, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
```
      Offending '(pend_req[h2d.a_source].pend == 0)'
  UVM_ERROR @ 18383.234466 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
  UVM_INFO @ 18383.234466 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.13701621400461480214081070356571590827514639021179307775275708908610093597111
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 3.474s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.6713266275218679546355606221133057636045578613111481604074270139171495371970
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.171s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.46959268104153101129055371530675230164363377961825013621832131736350227631729
    Line 827, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.84664601294201158093837179839426639348596535811446558390242514162902565347784
    Line 593, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.39237537256175437447901791458915468143930782774405421696312863096499076424758
    Line 770, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.53435664219878988561495648172573270271338084049679919703114897440697199020988
    Line 571, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.60232589095747512943948537443058017568125358724710875165214423334184205216492
    Line 430, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3113.739398 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3113.739398 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@95461) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.52006527483362008089616028984046706783952181758889824922833874507113382009186
Line 437, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4881.807330 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@95461) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4881.807330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.71023763556812182198798082528730612281078105889192694658271249904102232083435
    Line 415, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 10983.265650 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 10983.265650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.74880587005517989463507317040962511522976470855274745839695740817166873710153
    Line 438, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34730.560438 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34730.560438 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:382)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.24557831747382725316761103713443656447853063679361148193508809502094075280522
    Line 414, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3619.342580 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:382)] CHECK-fail: Expect alert 57!
  UVM_INFO @ 3619.342580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.69764013440168079958144731822510029598904557466334574520601989415107370970691
    Line 406, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3247.731548 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3247.731548 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.105056321021837542862305812129449339279289466500989277049718936674130905861051
    Line 407, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 3451.998912 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 3451.998912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35481) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.79364765385527848570804936221147010682058701798416248142730244466317544218869
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2162.086600 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35481) { a_addr: 'h106a4  a_data: 'hd0d6f825  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h27  a_opcode: 'h4  a_user: 'h1ba61  d_param: 'h0  d_source: 'h27  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2162.086600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(!$isunknown(alert_major_internal_o))' has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.9025117847050450437183562872385235747605765504629216913376470368977772732960
    Line 412, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
      Offending '(!$isunknown(alert_major_internal_o))'
  UVM_ERROR @ 1549.457055 us: (ibex_top.sv:1168) [ASSERT FAILED] IbexAlertMajorInternalX
  UVM_INFO @ 1549.457055 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.28435756693161144243512716455936640725709762956867970668284545366023277389581
    Line 414, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3095.555500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3095.555500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.99582141966033188541468977898106142504207781684563057771419640763756753441862
    Line 422, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3382.900000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3382.900000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.77646994800619898354345043845271434722069503149010155518056532398996106311673
    Line 429, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 25562.018193 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 25562.018193 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.78572354087760042142932551840749220038180589320402673286107225588680847925141
    Line 716, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.106346160767427649310147256045851586980967821759575154146552231412361817083626
    Line 559, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32113) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.4488954964676294700916309661685095899075019241398536790775815385546514983140
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2375.774328 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32113) { a_addr: 'h10674  a_data: 'hd77214bb  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3d  a_opcode: 'h4  a_user: 'h186a9  d_param: 'h0  d_source: 'h3d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2375.774328 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---