ADC_CTRL Simulation Results

Thursday May 15 2025 20:26:16 UTC

GitHub Revision: 608ba69

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	10.300s	5.762ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.740s	778.740us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.400s	470.756us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	40.320s	28.200ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.980s	1.013ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.340s	404.927us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.400s	470.756us	1	1	100.00
		adc_ctrl_csr_aliasing	3.980s	1.013ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	3.748m	326.958ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	4.726m	165.461ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	4.362m	163.363ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	1.009m	160.315ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	2.238m	173.487ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	14.808m	593.430ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	5.013m	335.199ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	1.893m	2.000s	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	3.240s	3.983ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	16.890s	41.742ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	1.641m	102.558ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	2.393m	341.773ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.530s	490.908us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.360s	447.393us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.110s	952.946us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.110s	952.946us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.740s	778.740us	1	1	100.00
		adc_ctrl_csr_rw	2.400s	470.756us	1	1	100.00
		adc_ctrl_csr_aliasing	3.980s	1.013ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.380s	4.677ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.740s	778.740us	1	1	100.00
		adc_ctrl_csr_rw	2.400s	470.756us	1	1	100.00
		adc_ctrl_csr_aliasing	3.980s	1.013ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.380s	4.677ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	2.910s	9.608ms	1	1	100.00
		adc_ctrl_tl_intg_err	8.520s	4.219ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	8.520s	4.219ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	3.920s	11.160ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.8185909986892357266289544513093032912125424110947977319197175386783009477856
      Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---