EDN Simulation Results

Thursday May 15 2025 20:26:16 UTC

GitHub Revision: 608ba69

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.800s	16.862us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.700s	147.419us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.700s	25.571us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.380s	398.414us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.820s	28.465us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.910s	56.286us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.700s	25.571us	1	1	100.00
		edn_csr_aliasing	1.820s	28.465us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.500s	118.593us	1	1	100.00
V2	csrng_commands	edn_genbits	2.500s	118.593us	1	1	100.00
V2	genbits	edn_genbits	2.500s	118.593us	1	1	100.00
V2	interrupts	edn_intr	1.950s	25.551us	1	1	100.00
V2	alerts	edn_alert	1.900s	24.539us	1	1	100.00
V2	errs	edn_err	1.910s	64.511us	1	1	100.00
V2	disable	edn_disable	1.750s	15.336us	1	1	100.00
		edn_disable_auto_req_mode	1.900s	65.575us	1	1	100.00
V2	stress_all	edn_stress_all	3.240s	275.344us	1	1	100.00
V2	intr_test	edn_intr_test	1.700s	16.267us	1	1	100.00
V2	alert_test	edn_alert_test	1.670s	16.354us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.750s	68.679us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.750s	68.679us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.700s	147.419us	1	1	100.00
		edn_csr_rw	1.700s	25.571us	1	1	100.00
		edn_csr_aliasing	1.820s	28.465us	1	1	100.00
		edn_same_csr_outstanding	1.920s	192.316us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.700s	147.419us	1	1	100.00
		edn_csr_rw	1.700s	25.571us	1	1	100.00
		edn_csr_aliasing	1.820s	28.465us	1	1	100.00
		edn_same_csr_outstanding	1.920s	192.316us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	9.120s	2.208ms	1	1	100.00
		edn_tl_intg_err	2.660s	134.226us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.710s	26.984us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.900s	24.539us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	9.120s	2.208ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	9.120s	2.208ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	9.120s	2.208ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	9.120s	2.208ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.900s	24.539us	1	1	100.00
		edn_sec_cm	9.120s	2.208ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.900s	24.539us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.660s	134.226us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.179m	16.397ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00