ENTROPY_SRC Simulation Results

Thursday May 15 2025 20:26:16 UTC

GitHub Revision: 608ba69

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 5.000s 100.165us 1 1 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 24.391us 1 1 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 96.631us 1 1 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 11.000s 519.841us 1 1 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 473.870us 1 1 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 6.000s 109.933us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 96.631us 1 1 100.00
entropy_src_csr_aliasing 8.000s 473.870us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware entropy_src_smoke 5.000s 100.165us 1 1 100.00
entropy_src_rng 9.000s 612.904us 0 1 0.00
entropy_src_fw_ov 5.533m 17.458ms 0 1 0.00
V2 firmware_mode entropy_src_fw_ov 5.533m 17.458ms 0 1 0.00
V2 rng_mode entropy_src_rng 9.000s 612.904us 0 1 0.00
V2 rng_max_rate entropy_src_rng_max_rate 6.000s 63.183us 0 1 0.00
V2 health_checks entropy_src_rng 9.000s 612.904us 0 1 0.00
V2 conditioning entropy_src_rng 9.000s 612.904us 0 1 0.00
V2 interrupts entropy_src_rng 9.000s 612.904us 0 1 0.00
entropy_src_intr 7.000s 177.632us 1 1 100.00
V2 alerts entropy_src_rng 9.000s 612.904us 0 1 0.00
entropy_src_functional_alerts 5.000s 204.854us 1 1 100.00
V2 stress_all entropy_src_stress_all 34.000s 8.985ms 1 1 100.00
V2 functional_errors entropy_src_functional_errors 4.000s 41.927us 1 1 100.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 12.000s 670.079us 1 1 100.00
V2 intr_test entropy_src_intr_test 4.000s 15.325us 1 1 100.00
V2 alert_test entropy_src_alert_test 4.000s 67.721us 1 1 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 5.000s 62.677us 1 1 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 5.000s 62.677us 1 1 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 24.391us 1 1 100.00
entropy_src_csr_rw 4.000s 96.631us 1 1 100.00
entropy_src_csr_aliasing 8.000s 473.870us 1 1 100.00
entropy_src_same_csr_outstanding 5.000s 202.022us 1 1 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 24.391us 1 1 100.00
entropy_src_csr_rw 4.000s 96.631us 1 1 100.00
entropy_src_csr_aliasing 8.000s 473.870us 1 1 100.00
entropy_src_same_csr_outstanding 5.000s 202.022us 1 1 100.00
V2 TOTAL 9 12 75.00
V2S tl_intg_err entropy_src_sec_cm 5.000s 60.586us 1 1 100.00
entropy_src_tl_intg_err 5.000s 116.845us 1 1 100.00
V2S sec_cm_config_regwen entropy_src_rng 9.000s 612.904us 0 1 0.00
entropy_src_cfg_regwen 4.000s 19.767us 1 1 100.00
V2S sec_cm_config_mubi entropy_src_rng 9.000s 612.904us 0 1 0.00
V2S sec_cm_config_redun entropy_src_rng 9.000s 612.904us 0 1 0.00
V2S sec_cm_intersig_mubi entropy_src_rng 9.000s 612.904us 0 1 0.00
entropy_src_fw_ov 5.533m 17.458ms 0 1 0.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 4.000s 41.927us 1 1 100.00
entropy_src_sec_cm 5.000s 60.586us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 4.000s 41.927us 1 1 100.00
entropy_src_sec_cm 5.000s 60.586us 1 1 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 9.000s 612.904us 0 1 0.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 4.000s 41.927us 1 1 100.00
entropy_src_sec_cm 5.000s 60.586us 1 1 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 4.000s 41.927us 1 1 100.00
entropy_src_sec_cm 5.000s 60.586us 1 1 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 4.000s 41.927us 1 1 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 204.854us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 5.000s 116.845us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 34.000s 2.007ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 18 22 81.82

Failure Buckets