HMAC Simulation Results

Thursday May 15 2025 20:26:16 UTC

GitHub Revision: 608ba69

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 9.350s 11.762ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.830s 88.391us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.770s 28.653us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 5.130s 1.943ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.440s 315.644us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 13.732m 325.064ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.770s 28.653us 1 1 100.00
hmac_csr_aliasing 3.440s 315.644us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 5.670s 436.702us 1 1 100.00
V2 back_pressure hmac_back_pressure 5.930s 931.201us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 9.000s 578.798us 1 1 100.00
hmac_test_sha384_vectors 5.524m 66.806ms 1 1 100.00
hmac_test_sha512_vectors 25.380s 543.342us 1 1 100.00
hmac_test_hmac256_vectors 10.210s 306.795us 1 1 100.00
hmac_test_hmac384_vectors 10.050s 348.817us 1 1 100.00
hmac_test_hmac512_vectors 9.280s 455.642us 1 1 100.00
V2 burst_wr hmac_burst_wr 4.180s 305.261us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 4.246m 9.958ms 1 1 100.00
V2 error hmac_error 36.430s 919.788us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 43.970s 1.353ms 1 1 100.00
V2 save_and_restore hmac_smoke 9.350s 11.762ms 1 1 100.00
hmac_long_msg 5.670s 436.702us 1 1 100.00
hmac_back_pressure 5.930s 931.201us 1 1 100.00
hmac_datapath_stress 4.246m 9.958ms 1 1 100.00
hmac_burst_wr 4.180s 305.261us 1 1 100.00
hmac_stress_all 25.430s 655.997us 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 9.350s 11.762ms 1 1 100.00
hmac_long_msg 5.670s 436.702us 1 1 100.00
hmac_back_pressure 5.930s 931.201us 1 1 100.00
hmac_datapath_stress 4.246m 9.958ms 1 1 100.00
hmac_wipe_secret 43.970s 1.353ms 1 1 100.00
hmac_test_sha256_vectors 9.000s 578.798us 1 1 100.00
hmac_test_sha384_vectors 5.524m 66.806ms 1 1 100.00
hmac_test_sha512_vectors 25.380s 543.342us 1 1 100.00
hmac_test_hmac256_vectors 10.210s 306.795us 1 1 100.00
hmac_test_hmac384_vectors 10.050s 348.817us 1 1 100.00
hmac_test_hmac512_vectors 9.280s 455.642us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 9.350s 11.762ms 1 1 100.00
hmac_long_msg 5.670s 436.702us 1 1 100.00
hmac_back_pressure 5.930s 931.201us 1 1 100.00
hmac_datapath_stress 4.246m 9.958ms 1 1 100.00
hmac_burst_wr 4.180s 305.261us 1 1 100.00
hmac_error 36.430s 919.788us 1 1 100.00
hmac_wipe_secret 43.970s 1.353ms 1 1 100.00
hmac_test_sha256_vectors 9.000s 578.798us 1 1 100.00
hmac_test_sha384_vectors 5.524m 66.806ms 1 1 100.00
hmac_test_sha512_vectors 25.380s 543.342us 1 1 100.00
hmac_test_hmac256_vectors 10.210s 306.795us 1 1 100.00
hmac_test_hmac384_vectors 10.050s 348.817us 1 1 100.00
hmac_test_hmac512_vectors 9.280s 455.642us 1 1 100.00
hmac_stress_all 25.430s 655.997us 1 1 100.00
V2 stress_all hmac_stress_all 25.430s 655.997us 1 1 100.00
V2 alert_test hmac_alert_test 1.580s 25.115us 1 1 100.00
V2 intr_test hmac_intr_test 1.640s 24.750us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.390s 57.247us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.390s 57.247us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.830s 88.391us 1 1 100.00
hmac_csr_rw 1.770s 28.653us 1 1 100.00
hmac_csr_aliasing 3.440s 315.644us 1 1 100.00
hmac_same_csr_outstanding 3.660s 295.429us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.830s 88.391us 1 1 100.00
hmac_csr_rw 1.770s 28.653us 1 1 100.00
hmac_csr_aliasing 3.440s 315.644us 1 1 100.00
hmac_same_csr_outstanding 3.660s 295.429us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.070s 1.216ms 1 1 100.00
hmac_tl_intg_err 2.550s 321.859us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.550s 321.859us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 9.350s 11.762ms 1 1 100.00
V3 stress_reset hmac_stress_reset 2.170s 56.106us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.783m 14.743ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 4.020s 558.090us 1 1 100.00
TOTAL 28 28 100.00