I2C Simulation Results

Thursday May 15 2025 20:26:16 UTC

GitHub Revision: 608ba69

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	51.440s	5.698ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	14.840s	5.657ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.570s	20.985us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.660s	26.370us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.790s	236.969us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.370s	443.607us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.560s	43.075us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.660s	26.370us	1	1	100.00
		i2c_csr_aliasing	2.370s	443.607us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.250s	379.129us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	4.663m	59.641ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	3.312m	12.024ms	1	1	100.00
V2	host_override	i2c_host_override	1.510s	25.358us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	53.170s	13.203ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	38.480s	2.559ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.910s	275.833us	1	1	100.00
		i2c_host_fifo_fmt_empty	7.370s	625.648us	1	1	100.00
		i2c_host_fifo_reset_rx	4.150s	204.369us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	46.230s	5.704ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	8.700s	701.193us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.260s	298.452us	1	1	100.00
V2	target_glitch	i2c_target_glitch	8.490s	10.361ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	48.170s	66.751ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.870s	568.590us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	12.580s	4.150ms	1	1	100.00
		i2c_target_intr_smoke	3.570s	2.509ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.920s	181.012us	1	1	100.00
		i2c_target_fifo_reset_tx	1.850s	198.807us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.660m	52.625ms	1	1	100.00
		i2c_target_stress_rd	12.580s	4.150ms	1	1	100.00
		i2c_target_intr_stress_wr	2.112m	13.704ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.400s	3.044ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	2.320s	208.264us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.340s	3.719ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	10.700s	10.386ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.930s	581.506us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.900s	383.851us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	3.312m	12.024ms	1	1	100.00
		i2c_host_perf_precise	2.040s	279.792us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	8.700s	701.193us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	5.350s	404.934us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.770s	513.437us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.700s	2.577ms	1	1	100.00
		i2c_target_nack_txstretch	1.920s	132.260us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	14.000s	499.634us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.590s	472.204us	1	1	100.00
V2	alert_test	i2c_alert_test	1.620s	44.633us	1	1	100.00
V2	intr_test	i2c_intr_test	1.630s	20.799us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.370s	52.369us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.370s	52.369us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.570s	20.985us	1	1	100.00
		i2c_csr_rw	1.660s	26.370us	1	1	100.00
		i2c_csr_aliasing	2.370s	443.607us	1	1	100.00
		i2c_same_csr_outstanding	1.920s	225.778us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.570s	20.985us	1	1	100.00
		i2c_csr_rw	1.660s	26.370us	1	1	100.00
		i2c_csr_aliasing	2.370s	443.607us	1	1	100.00
		i2c_same_csr_outstanding	1.920s	225.778us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.150s	70.691us	1	1	100.00
		i2c_sec_cm	1.680s	47.500us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.150s	70.691us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	9.690s	609.790us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.690s	36.626us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	2.050s	95.000us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.32939943580680207473515409803161255010914393304143877099724790607419902604708
      Line 203, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 59640818003 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @2796646
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.56844988962038443682934052699600189032812681278226364734213356619863817390135
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  36625746 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 2 [0x2])
        UVM_INFO @  36625746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.64121132063004543747515417742102947663027080700776460887431926907834322621249
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10386426212 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10386426212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.54505315093835638097734343591776851800031657217910786160603738595723710037818
      Line 90, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 609790406 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 609790406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.102650855982982346994026197248989967259442518869082024757911948293461507734219
      Line 91, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  95000340 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
        UVM_INFO @  95000340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.28351585282798751542137653955635834740018061153034501949207166193751339750524
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 132260013 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 132260013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---