KEYMGR Simulation Results

Thursday May 15 2025 20:26:16 UTC

GitHub Revision: 608ba69

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.600s	30.338us	1	1	100.00
V1	random	keymgr_random	19.850s	2.245ms	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.000s	65.758us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.960s	15.705us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	8.470s	347.548us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	5.640s	142.543us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.630s	24.960us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.960s	15.705us	1	1	100.00
		keymgr_csr_aliasing	5.640s	142.543us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	3.320s	78.174us	1	1	100.00
V2	sideload	keymgr_sideload	3.600s	99.631us	1	1	100.00
		keymgr_sideload_kmac	12.450s	2.445ms	1	1	100.00
		keymgr_sideload_aes	2.890s	306.525us	1	1	100.00
		keymgr_sideload_otbn	3.470s	389.265us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	11.280s	1.303ms	1	1	100.00
V2	lc_disable	keymgr_lc_disable	5.900s	172.960us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	4.170s	228.642us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	5.680s	242.742us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	4.210s	486.000us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.390s	266.641us	1	1	100.00
V2	stress_all	keymgr_stress_all	15.840s	3.723ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.860s	23.677us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.810s	15.519us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.840s	43.966us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.840s	43.966us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.000s	65.758us	1	1	100.00
		keymgr_csr_rw	1.960s	15.705us	1	1	100.00
		keymgr_csr_aliasing	5.640s	142.543us	1	1	100.00
		keymgr_same_csr_outstanding	2.040s	106.515us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.000s	65.758us	1	1	100.00
		keymgr_csr_rw	1.960s	15.705us	1	1	100.00
		keymgr_csr_aliasing	5.640s	142.543us	1	1	100.00
		keymgr_same_csr_outstanding	2.040s	106.515us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	8.260s	409.133us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	8.260s	409.133us	1	1	100.00
		keymgr_tl_intg_err	3.300s	192.481us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.230s	147.703us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.230s	147.703us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.230s	147.703us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.230s	147.703us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	4.570s	138.522us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	8.260s	409.133us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	8.260s	409.133us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.300s	192.481us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.230s	147.703us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.320s	78.174us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	19.850s	2.245ms	1	1	100.00
		keymgr_csr_rw	1.960s	15.705us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	19.850s	2.245ms	1	1	100.00
		keymgr_csr_rw	1.960s	15.705us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	19.850s	2.245ms	1	1	100.00
		keymgr_csr_rw	1.960s	15.705us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	5.900s	172.960us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	4.210s	486.000us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	4.210s	486.000us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	19.850s	2.245ms	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.130s	95.855us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	8.260s	409.133us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	8.260s	409.133us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	8.260s	409.133us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	4.160s	170.855us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	5.900s	172.960us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	8.260s	409.133us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	8.260s	409.133us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	8.260s	409.133us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	4.160s	170.855us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	4.160s	170.855us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	8.260s	409.133us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	4.160s	170.855us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	8.260s	409.133us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	4.160s	170.855us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	12.900s	1.106ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test keymgr_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.keymgr_csr_mem_rw_with_rand_reset.13827175794984647490983948626372404835363719333899066242066530049984592446907
      Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
        UVM_ERROR @  24959542 ps: (keymgr_csr_assert_fpv.sv:464) [ASSERT FAILED] attest_sw_binding_6_rd_A
        UVM_INFO @  24959542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---