KMAC/MASKED Simulation Results

Thursday May 15 2025 20:26:16 UTC

GitHub Revision: 608ba69

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	14.090s	729.630us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.680s	64.934us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.660s	57.792us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	9.460s	2.012ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.810s	1.044ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.720s	155.559us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.660s	57.792us	1	1	100.00
		kmac_csr_aliasing	6.810s	1.044ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.620s	18.306us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.110s	56.515us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	21.801m	69.290ms	1	1	100.00
V2	burst_write	kmac_burst_write	3.671m	27.223ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.156m	113.575ms	1	1	100.00
		kmac_test_vectors_sha3_256	27.300s	3.954ms	1	1	100.00
		kmac_test_vectors_sha3_384	22.432m	46.575ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.180s	3.827ms	1	1	100.00
		kmac_test_vectors_shake_128	37.295m	389.853ms	1	1	100.00
		kmac_test_vectors_shake_256	5.217m	89.569ms	1	1	100.00
		kmac_test_vectors_kmac	3.780s	377.130us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.090s	101.231us	1	1	100.00
V2	sideload	kmac_sideload	2.691m	24.293ms	1	1	100.00
V2	app	kmac_app	4.981m	183.813ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	32.520s	2.169ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.042m	4.078ms	1	1	100.00
V2	error	kmac_error	4.667m	19.640ms	1	1	100.00
V2	key_error	kmac_key_error	9.910s	1.800ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	7.830s	1.448ms	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.790s	25.851us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.810s	44.277us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.082m	7.652ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.090s	46.472us	1	1	100.00
V2	stress_all	kmac_stress_all	28.618m	235.586ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.760s	22.071us	1	1	100.00
V2	alert_test	kmac_alert_test	1.850s	32.276us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.640s	614.837us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.640s	614.837us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.680s	64.934us	1	1	100.00
		kmac_csr_rw	1.660s	57.792us	1	1	100.00
		kmac_csr_aliasing	6.810s	1.044ms	1	1	100.00
		kmac_same_csr_outstanding	2.140s	94.672us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.680s	64.934us	1	1	100.00
		kmac_csr_rw	1.660s	57.792us	1	1	100.00
		kmac_csr_aliasing	6.810s	1.044ms	1	1	100.00
		kmac_same_csr_outstanding	2.140s	94.672us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.110s	59.572us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.110s	59.572us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.110s	59.572us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.110s	59.572us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.010s	25.786us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	42.760s	9.003ms	1	1	100.00
		kmac_tl_intg_err	3.820s	175.110us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.820s	175.110us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.090s	46.472us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	14.090s	729.630us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.691m	24.293ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.110s	59.572us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	42.760s	9.003ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	42.760s	9.003ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	42.760s	9.003ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	14.090s	729.630us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.090s	46.472us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	42.760s	9.003ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.480m	130.565ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	14.090s	729.630us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.620s	174.878us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.70912101601202117384430187536811327963032240512490783049502597644841576055293
      Line 80, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 174877824 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 174877824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.6704285222642002234423485975681104914563204015991352560390604270042360540512
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
        UVM_ERROR @  25785618 ps: (kmac_csr_assert_fpv.sv:515) [ASSERT FAILED] prefix_4_rd_A
        UVM_INFO @  25785618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---