KMAC/UNMASKED Simulation Results

Thursday May 15 2025 20:26:16 UTC

GitHub Revision: 608ba69

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	23.750s	6.479ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.890s	53.804us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.800s	37.771us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.600s	6.003ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.080s	261.057us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.710s	146.276us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.800s	37.771us	1	1	100.00
		kmac_csr_aliasing	4.080s	261.057us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.690s	44.252us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.120s	67.510us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	11.809m	369.717ms	1	1	100.00
V2	burst_write	kmac_burst_write	6.285m	6.200ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.800s	6.049ms	1	1	100.00
		kmac_test_vectors_sha3_256	22.737m	118.517ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.260s	1.220ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.300s	2.895ms	1	1	100.00
		kmac_test_vectors_shake_128	2.163m	20.380ms	1	1	100.00
		kmac_test_vectors_shake_256	4.446m	47.803ms	1	1	100.00
		kmac_test_vectors_kmac	2.760s	103.169us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.190s	382.779us	1	1	100.00
V2	sideload	kmac_sideload	3.749m	21.420ms	1	1	100.00
V2	app	kmac_app	2.956m	11.187ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.083m	9.731ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.492m	19.517ms	1	1	100.00
V2	error	kmac_error	2.510m	3.667ms	1	1	100.00
V2	key_error	kmac_key_error	3.350s	518.902us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.030s	617.828us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	28.450s	13.666ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	4.160s	878.479us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	2.520s	88.434us	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.140s	39.397us	1	1	100.00
V2	stress_all	kmac_stress_all	7.647m	50.288ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.530s	18.232us	1	1	100.00
V2	alert_test	kmac_alert_test	1.710s	24.858us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.780s	94.249us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.780s	94.249us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.890s	53.804us	1	1	100.00
		kmac_csr_rw	1.800s	37.771us	1	1	100.00
		kmac_csr_aliasing	4.080s	261.057us	1	1	100.00
		kmac_same_csr_outstanding	1.900s	136.734us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.890s	53.804us	1	1	100.00
		kmac_csr_rw	1.800s	37.771us	1	1	100.00
		kmac_csr_aliasing	4.080s	261.057us	1	1	100.00
		kmac_same_csr_outstanding	1.900s	136.734us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.760s	228.360us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.760s	228.360us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.760s	228.360us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.760s	228.360us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.810s	104.600us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	25.820s	2.365ms	1	1	100.00
		kmac_tl_intg_err	1.750s	39.082us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.750s	39.082us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.140s	39.397us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	23.750s	6.479ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.749m	21.420ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.760s	228.360us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	25.820s	2.365ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	25.820s	2.365ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	25.820s	2.365ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	23.750s	6.479ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.140s	39.397us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	25.820s	2.365ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.681m	20.989ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	23.750s	6.479ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	59.190s	10.414ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.53889163525234681340394847641726279482645261842075554238113280789956301304155
      Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
        UVM_ERROR @  39082174 ps: (kmac_csr_assert_fpv.sv:515) [ASSERT FAILED] prefix_4_rd_A
        UVM_INFO @  39082174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---