ROM_CTRL/32KB Simulation Results

Thursday May 15 2025 20:26:16 UTC

GitHub Revision: 608ba69

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.600s 455.269us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.170s 285.766us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.140s 349.112us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.740s 170.160us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.250s 1.220ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.430s 333.531us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.140s 349.112us 1 1 100.00
rom_ctrl_csr_aliasing 4.250s 1.220ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 5.140s 170.133us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.810s 299.056us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.470s 139.867us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 10.660s 610.536us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 8.590s 569.275us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.960s 269.138us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.800s 585.437us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.800s 585.437us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.170s 285.766us 1 1 100.00
rom_ctrl_csr_rw 4.140s 349.112us 1 1 100.00
rom_ctrl_csr_aliasing 4.250s 1.220ms 1 1 100.00
rom_ctrl_same_csr_outstanding 5.670s 167.262us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.170s 285.766us 1 1 100.00
rom_ctrl_csr_rw 4.140s 349.112us 1 1 100.00
rom_ctrl_csr_aliasing 4.250s 1.220ms 1 1 100.00
rom_ctrl_same_csr_outstanding 5.670s 167.262us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.055m 9.377ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 13.090s 1.486ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.192m 1.476ms 1 1 100.00
rom_ctrl_tl_intg_err 46.870s 392.192us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.192m 1.476ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 3.192m 1.476ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.055m 9.377ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.055m 9.377ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.055m 9.377ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.055m 9.377ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.055m 9.377ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.192m 1.476ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.192m 1.476ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.600s 455.269us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.600s 455.269us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.600s 455.269us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 46.870s 392.192us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.055m 9.377ms 1 1 100.00
rom_ctrl_kmac_err_chk 8.590s 569.275us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.055m 9.377ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.055m 9.377ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.055m 9.377ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 13.090s 1.486ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.192m 1.476ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 52.390s 2.037ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00