ROM_CTRL/64KB Simulation Results

Thursday May 15 2025 20:26:16 UTC

GitHub Revision: 608ba69

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.720s 223.531us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.630s 223.918us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.040s 370.011us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 10.600s 2.485ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 8.090s 288.800us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 8.080s 1.356ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.040s 370.011us 1 1 100.00
rom_ctrl_csr_aliasing 8.090s 288.800us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.950s 1.072ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.000s 210.059us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.220s 1.096ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 29.140s 1.070ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 13.400s 2.644ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 5.880s 650.798us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.310s 3.561ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.310s 3.561ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.630s 223.918us 1 1 100.00
rom_ctrl_csr_rw 6.040s 370.011us 1 1 100.00
rom_ctrl_csr_aliasing 8.090s 288.800us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.120s 535.027us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.630s 223.918us 1 1 100.00
rom_ctrl_csr_rw 6.040s 370.011us 1 1 100.00
rom_ctrl_csr_aliasing 8.090s 288.800us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.120s 535.027us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.795m 4.879ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 26.270s 3.782ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.612m 4.658ms 1 1 100.00
rom_ctrl_tl_intg_err 1.138m 1.612ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.612m 4.658ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.612m 4.658ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.795m 4.879ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.795m 4.879ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.795m 4.879ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.795m 4.879ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.795m 4.879ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.612m 4.658ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.612m 4.658ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.720s 223.531us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.720s 223.531us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.720s 223.531us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.138m 1.612ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.795m 4.879ms 1 1 100.00
rom_ctrl_kmac_err_chk 13.400s 2.644ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.795m 4.879ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.795m 4.879ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.795m 4.879ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 26.270s 3.782ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.612m 4.658ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.601m 3.256ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00