RV_DM/USE_JTAG_INTERFACE Simulation Results

Thursday May 15 2025 20:26:16 UTC

GitHub Revision: 608ba69

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 9.050s 4.246ms 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 2.130s 319.106us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 3.180s 923.860us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 6.830s 4.859ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 3.090s 772.664us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 11.730s 5.505ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 8.970s 4.334ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 4.520s 3.675ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 2.566m 83.069ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.990s 385.488us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.460s 120.348us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.000s 344.636us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.760s 141.542us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.840s 147.486us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 2.090s 625.744us 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.630s 86.675us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 1.600s 625.429us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.990s 385.488us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.940s 598.418us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.840s 480.365us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.000s 344.636us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.810s 119.915us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.930s 395.275us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.270s 83.791us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 57.820s 29.137ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 17.080s 1.104ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.670s 20.863us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 17.080s 1.104ms 1 1 100.00
rv_dm_csr_rw 2.270s 83.791us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.520s 26.873us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.610s 87.673us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 9.050s 4.246ms 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.900s 609.118us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.800s 451.937us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.810s 128.840us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.990s 890.130us 1 1 100.00
V2 sba rv_dm_sba_tl_access 4.810s 3.482ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 2.190s 424.945us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 4.160s 1.600ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 11.510s 11.027ms 1 1 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.670s 378.522us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 7.210s 3.602ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.590s 270.236us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.700s 116.027us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 8.380s 11.861ms 0 1 0.00
rv_dm_tap_fsm_rand_reset 2.420s 289.052us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.820s 147.589us 1 1 100.00
V2 stress_all rv_dm_stress_all 8.090s 5.570ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.570s 40.593us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 4.710s 1.020ms 1 1 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 4.710s 1.020ms 1 1 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 17.080s 1.104ms 1 1 100.00
rv_dm_csr_hw_reset 2.930s 395.275us 1 1 100.00
rv_dm_csr_rw 2.270s 83.791us 1 1 100.00
rv_dm_same_csr_outstanding 6.480s 568.621us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 17.080s 1.104ms 1 1 100.00
rv_dm_csr_hw_reset 2.930s 395.275us 1 1 100.00
rv_dm_csr_rw 2.270s 83.791us 1 1 100.00
rv_dm_same_csr_outstanding 6.480s 568.621us 1 1 100.00
V2 TOTAL 16 19 84.21
V2S tl_intg_err rv_dm_sec_cm 1.800s 957.785us 1 1 100.00
rv_dm_tl_intg_err 13.380s 7.742ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 13.380s 7.742ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 7.210s 3.602ms 1 1 100.00
rv_dm_debug_disabled 1.890s 72.140us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 7.210s 3.602ms 1 1 100.00
rv_dm_debug_disabled 1.890s 72.140us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 9.050s 4.246ms 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 1.910s 417.344us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.780s 202.308us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.780s 202.308us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 1.910s 417.344us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.880s 88.309us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.520s 32.439us 1 1 100.00
TOTAL 48 53 90.57

Failure Buckets